Abstract
We present a technique for thinning the channel region of silicon nanowires (SiNWs) selectively while maintaining a thickness of the source/drain (S/D) regions in an attempt to minimize the parasitic series resistance of SiNW transistors (SNWTs). By transferring the as-fabricated SiNWs onto a plastic substrate, p-SNWTs were fabricated on a plastic substrate, and carrier transport in p-SNWTs was investigated by extracting electrical parameters using the YΦ method, which include mobility attenuation factors, parasitic series resistance (R sd), and effective channel resistance. It is shown that, in the strong inversion region, the parameters fit the measurement data well and that degradation in device performance in our p-SNWTs under high transverse electric fields is dominated by surface roughness scattering, with minimal R sd impact on it due to the relatively thick S/D regions.
| Original language | English |
|---|---|
| Article number | 093503 |
| Journal | Applied Physics Letters |
| Volume | 101 |
| Issue number | 9 |
| DOIs | |
| Publication status | Published - 2012 Aug 27 |
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ASJC Scopus subject areas
- Physics and Astronomy (miscellaneous)
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Analysis of electrical parameters of p-channel silicon nanowire transistors with selectively thinned channels on plastics. / Lee, M.; Jeon, Y.; Kim, Sangsig.
In: Applied Physics Letters, Vol. 101, No. 9, 093503, 27.08.2012.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Analysis of electrical parameters of p-channel silicon nanowire transistors with selectively thinned channels on plastics
AU - Lee, M.
AU - Jeon, Y.
AU - Kim, Sangsig
PY - 2012/8/27
Y1 - 2012/8/27
N2 - We present a technique for thinning the channel region of silicon nanowires (SiNWs) selectively while maintaining a thickness of the source/drain (S/D) regions in an attempt to minimize the parasitic series resistance of SiNW transistors (SNWTs). By transferring the as-fabricated SiNWs onto a plastic substrate, p-SNWTs were fabricated on a plastic substrate, and carrier transport in p-SNWTs was investigated by extracting electrical parameters using the YΦ method, which include mobility attenuation factors, parasitic series resistance (R sd), and effective channel resistance. It is shown that, in the strong inversion region, the parameters fit the measurement data well and that degradation in device performance in our p-SNWTs under high transverse electric fields is dominated by surface roughness scattering, with minimal R sd impact on it due to the relatively thick S/D regions.
AB - We present a technique for thinning the channel region of silicon nanowires (SiNWs) selectively while maintaining a thickness of the source/drain (S/D) regions in an attempt to minimize the parasitic series resistance of SiNW transistors (SNWTs). By transferring the as-fabricated SiNWs onto a plastic substrate, p-SNWTs were fabricated on a plastic substrate, and carrier transport in p-SNWTs was investigated by extracting electrical parameters using the YΦ method, which include mobility attenuation factors, parasitic series resistance (R sd), and effective channel resistance. It is shown that, in the strong inversion region, the parameters fit the measurement data well and that degradation in device performance in our p-SNWTs under high transverse electric fields is dominated by surface roughness scattering, with minimal R sd impact on it due to the relatively thick S/D regions.
UR - http://www.scopus.com/inward/record.url?scp=84865854839&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84865854839&partnerID=8YFLogxK
U2 - 10.1063/1.4747812
DO - 10.1063/1.4747812
M3 - Article
AN - SCOPUS:84865854839
VL - 101
JO - Applied Physics Letters
JF - Applied Physics Letters
SN - 0003-6951
IS - 9
M1 - 093503
ER -