Analysis of electrical parameters of p-channel silicon nanowire transistors with selectively thinned channels on plastics

M. Lee, Y. Jeon, Sangsig Kim

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

We present a technique for thinning the channel region of silicon nanowires (SiNWs) selectively while maintaining a thickness of the source/drain (S/D) regions in an attempt to minimize the parasitic series resistance of SiNW transistors (SNWTs). By transferring the as-fabricated SiNWs onto a plastic substrate, p-SNWTs were fabricated on a plastic substrate, and carrier transport in p-SNWTs was investigated by extracting electrical parameters using the YΦ method, which include mobility attenuation factors, parasitic series resistance (R sd), and effective channel resistance. It is shown that, in the strong inversion region, the parameters fit the measurement data well and that degradation in device performance in our p-SNWTs under high transverse electric fields is dominated by surface roughness scattering, with minimal R sd impact on it due to the relatively thick S/D regions.

Original languageEnglish
Article number093503
JournalApplied Physics Letters
Volume101
Issue number9
DOIs
Publication statusPublished - 2012 Aug 27

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nanowires
transistors
plastics
silicon
surface roughness
attenuation
inversions
degradation
electric fields
scattering

ASJC Scopus subject areas

  • Physics and Astronomy (miscellaneous)

Cite this

Analysis of electrical parameters of p-channel silicon nanowire transistors with selectively thinned channels on plastics. / Lee, M.; Jeon, Y.; Kim, Sangsig.

In: Applied Physics Letters, Vol. 101, No. 9, 093503, 27.08.2012.

Research output: Contribution to journalArticle

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