Abstract
The energy distribution and density of interface traps (Dit) are directly investigated from bulk-type and thin-film transistor (TFT)-type charge trap flash memory cells with tunnel oxide degradation, under program/erase (P/E) cycling using a charge pumping (CP) technique, in view of application in a 3-demension stackable NAND flash memory cell. After P/E cycling in bulk-type devices, the interface trap density gradually increased from 1.55 × 1012 cm-2 eV-1 to 3.66 × 1013 cm-2 eV-1 due to tunnel oxide damage, which was consistent with the subthreshold swing and transconductance degradation after P/E cycling. Its distribution moved toward shallow energy levels with increasing cycling numbers, which coincided with the decay rate degradation with short-term retention time. The tendency extracted with the CP technique for Dit of the TFT-type cells was similar to those of bulk-type cells.
Original language | English |
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Pages (from-to) | 5084-5087 |
Number of pages | 4 |
Journal | Materials Research Bulletin |
Volume | 48 |
Issue number | 12 |
DOIs | |
Publication status | Published - 2013 |
Keywords
- 3D NAND
- CTF
- Charge pumping technique
- SONOS
ASJC Scopus subject areas
- Materials Science(all)
- Condensed Matter Physics
- Mechanics of Materials
- Mechanical Engineering