TY - GEN
T1 - Analytical calculation and fabrication of FET-embedded capacitive micromachined ultrasonic transducer
AU - Park, Jin Soo
AU - Kim, Jung Yeon
AU - Bae, Hee Kyoung
AU - Kim, Jinsik
AU - Hwang, Kyo Seon
AU - Park, Jung Ho
AU - Choi, Rino
AU - Lee, Byung Chul
N1 - Funding Information:
ACKNOWLEDGMENT This work was supported by the KIST institutional program (2E26180) and Nano͎ Material Technology Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (2015M3A7B7045470). The FET part and low temperature wafer bonding processes were done at Korea National Nanofab Center (NNFC, Daejeon, South Korea) and other post fabrication processes were executed at KIST Micro-Nano Fabrication Center (Seoul, South Korea).
Publisher Copyright:
© 2017 IEEE.
PY - 2017/10/31
Y1 - 2017/10/31
N2 - In IUS 2016, we proposed a capacitive micromachined ultrasonic transducer embedded a field effect transistor (CMUT-FET) for 20 MHz operation. As a result, the possibility of high sensitivity in a high-frequency range was verified via a combination of two simulation tools, a 3-D finite element analysis (FEA) for the CMUT part and a technology computer aided design for the FET part. Since the results were acquired from the separate models, the exact voltage drop of the channel capacitance in the FET part was not considered into the CMUT simulation part. In this paper, we suggest a full analytic model which can simulate the whole CMUT-FET model with high accuracy and fast computation. As a consecutive work, we also report on a fabrication process of the CMUT-FET with nickel silicide source/drain contacts and low-temperature wafer bonding. Since high-temperature process on the upper CMUT during direct wafer bonding critically affects the performance of the lower FET, several low-temperature direct wafer bondings were attempted and the results were demonstrated in this paper.
AB - In IUS 2016, we proposed a capacitive micromachined ultrasonic transducer embedded a field effect transistor (CMUT-FET) for 20 MHz operation. As a result, the possibility of high sensitivity in a high-frequency range was verified via a combination of two simulation tools, a 3-D finite element analysis (FEA) for the CMUT part and a technology computer aided design for the FET part. Since the results were acquired from the separate models, the exact voltage drop of the channel capacitance in the FET part was not considered into the CMUT simulation part. In this paper, we suggest a full analytic model which can simulate the whole CMUT-FET model with high accuracy and fast computation. As a consecutive work, we also report on a fabrication process of the CMUT-FET with nickel silicide source/drain contacts and low-temperature wafer bonding. Since high-temperature process on the upper CMUT during direct wafer bonding critically affects the performance of the lower FET, several low-temperature direct wafer bondings were attempted and the results were demonstrated in this paper.
UR - http://www.scopus.com/inward/record.url?scp=85039459300&partnerID=8YFLogxK
U2 - 10.1109/ULTSYM.2017.8092863
DO - 10.1109/ULTSYM.2017.8092863
M3 - Conference contribution
AN - SCOPUS:85039459300
T3 - IEEE International Ultrasonics Symposium, IUS
BT - 2017 IEEE International Ultrasonics Symposium, IUS 2017
PB - IEEE Computer Society
T2 - 2017 IEEE International Ultrasonics Symposium, IUS 2017
Y2 - 6 September 2017 through 9 September 2017
ER -