Architecting large-scale SRAM arrays with monolithic 3D integration

Joonho Kong, Young Ho Gong, Sung Woo Jung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

In this paper, we architect large-scale SRAM arrays with monolithic 3D (M3D) integration technology. We introduce M3D-based SRAM arrays with three different ways of integration: M3D-R (vertical routing-only), M3D-VBL (vertical bitline), and M3D-VWL (vertical wordline). We also apply M3D-based SRAM arrays to last-level caches: Tag arrays for eDRAM LLCs and data arrays for SRAM LLCs. The proposed LLCs with M3D-based SRAM arrays lead to better performance and lower energy by 0.02%∼1.7% and 49.1%∼79.1%, respectively, compared to that with TSV-based 3D SRAM arrays.

Original languageEnglish
Title of host publicationISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509060238
DOIs
Publication statusPublished - 2017 Aug 11
Event22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017 - Taipei, Taiwan, Province of China
Duration: 2017 Jul 242017 Jul 26

Other

Other22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017
CountryTaiwan, Province of China
CityTaipei
Period17/7/2417/7/26

Keywords

  • Energy
  • Last-Level Caches
  • Monolithic 3D Integrations
  • Performance

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Kong, J., Gong, Y. H., & Jung, S. W. (2017). Architecting large-scale SRAM arrays with monolithic 3D integration. In ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design [8009157] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISLPED.2017.8009157