Back biasing effects in tri-gate junctionless transistors

So Jeong Park, Dae Young Jeon, Laurent Montès, Sylvain Barraud, Gyu-Tae Kim, Gérard Ghibaudo

Research output: Contribution to journalArticle

22 Citations (Scopus)

Abstract

The back bias effect on tri-gate junctionless transistors (JLTs) has been investigated using experimental results and 2-D numerical simulations, compared to inversion-mode (IM) transistors. Results show that JLT devices are more sensitive to back biasing due to the bulk conduction. It is also shown that the effective mobility of JLT is significantly enhanced below flat band voltage by back bias. However, in extremely narrow JLTs, the back bias effect is suppressed by reduced portion of bulk conduction and strong sidewall gate controls. 2-D numerical charge simulation well supports experimental results by reconstructing the trend of back bias effects.

Original languageEnglish
Pages (from-to)74-79
Number of pages6
JournalSolid-State Electronics
Volume87
DOIs
Publication statusPublished - 2013 Jul 11

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Keywords

  • 2-D numerical simulation
  • Back bias effect
  • Channel width variation
  • Junctionless transistor
  • SOI (silicon on insulator)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics
  • Electronic, Optical and Magnetic Materials
  • Materials Chemistry

Cite this

Park, S. J., Jeon, D. Y., Montès, L., Barraud, S., Kim, G-T., & Ghibaudo, G. (2013). Back biasing effects in tri-gate junctionless transistors. Solid-State Electronics, 87, 74-79. https://doi.org/10.1016/j.sse.2013.06.004