Binary decision diagram to design balanced secure logic styles

Hyunmin Kim, Seokhie Hong, Bart Preneel, Ingrid Verbauwhede

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Embedded implementations of cryptographic algorithms require countermeasures against side-channel attacks (SCAs), that exploit physical variables measured during the computation. These countermeasures increase cost, power consumption and latency of the device. One class of countermeasures, hiding, consists of a balanced circuit style, including balancing of the capacitances and delays; it requires full connection to avoid memory effect that is an effect caused by repeatedly recharged energy after being only partially discharged at the internal parasitic capacitance. This paper proposes binary decision diagrams (BDDs) to derive complex pull-down networks that fulfill all these requirements while being compact at the same time; it uses sense amplifier-based logic (SABL) to obtain well-balanced pre-charge circuits. An attack based on mutual information analysis (MIA) is applied to the AES S-boxes implemented in our novel secure logic style. After the evaluation at pre-layout SPICE level, the balanced circuit with BDD leaks less information than comparable logic styles, even though the implementation area is reduced by 40.6%, the power consumption up to 46.1% and the delay by 35.2% compared to the classic SABL approach.

Original languageEnglish
Title of host publication2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages239-244
Number of pages6
ISBN (Electronic)9781509015061
DOIs
Publication statusPublished - 2016 Oct 20
Event22nd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2016 - Sant Feliu de Guixols, Catalunya, Spain
Duration: 2016 Jul 42016 Jul 6

Other

Other22nd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2016
CountrySpain
CitySant Feliu de Guixols, Catalunya
Period16/7/416/7/6

Fingerprint

Binary decision diagrams
Networks (circuits)
Electric power utilization
Capacitance
Information analysis
SPICE
Data storage equipment
Costs

ASJC Scopus subject areas

  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality
  • Computer Networks and Communications

Cite this

Kim, H., Hong, S., Preneel, B., & Verbauwhede, I. (2016). Binary decision diagram to design balanced secure logic styles. In 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016 (pp. 239-244). [7604710] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IOLTS.2016.7604710

Binary decision diagram to design balanced secure logic styles. / Kim, Hyunmin; Hong, Seokhie; Preneel, Bart; Verbauwhede, Ingrid.

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 239-244 7604710.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kim, H, Hong, S, Preneel, B & Verbauwhede, I 2016, Binary decision diagram to design balanced secure logic styles. in 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016., 7604710, Institute of Electrical and Electronics Engineers Inc., pp. 239-244, 22nd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2016, Sant Feliu de Guixols, Catalunya, Spain, 16/7/4. https://doi.org/10.1109/IOLTS.2016.7604710
Kim H, Hong S, Preneel B, Verbauwhede I. Binary decision diagram to design balanced secure logic styles. In 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 239-244. 7604710 https://doi.org/10.1109/IOLTS.2016.7604710
Kim, Hyunmin ; Hong, Seokhie ; Preneel, Bart ; Verbauwhede, Ingrid. / Binary decision diagram to design balanced secure logic styles. 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 239-244
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