Abstract
This paper presents a low area and energy efficient hardware accelerator for the deep convolutional neural networks (CNNs). Based on the multiply-accumulate (MAC) based architecture, three design techniques are proposed to reduce the hardware cost of the convolutional computations. First, to reduce the computational bit-width of convolutions, an adaptive bit-width reduction scheme is proposed based on differential input method. The bit-width reduction approach can reduce the 37 % of operation bit-width with almost ignorable CNN accuracy degradation. Second, it has been found that adapting bi-directional filtering window in CNN accelerator can considerably reduce the energy for data movement with much smaller number of memory accesses. To expedite the bi-directional filtering operations, we also propose a bidirectional first-input-first-output (bi-FIFO). With SRAM bit-cell layout manner, the proposed bi-FIFO facilitates fast data re-distribution with area and energy efficiency. To verify the effectiveness of the proposed techniques, the AlexNet accelerator has been designed. The numerical results show that the proposed adaptive bit-width reduction scheme achieves 25.9% and 47.3% of area and energy savings, respectively. The bi-FIFO based accelerator also achieves 33 % improved processing time.
| Original language | English |
|---|---|
| Title of host publication | ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781509060238 |
| DOIs | |
| Publication status | Published - 2017 Aug 11 |
| Event | 22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017 - Taipei, Taiwan, Province of China Duration: 2017 Jul 24 → 2017 Jul 26 |
Other
| Other | 22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017 |
|---|---|
| Country | Taiwan, Province of China |
| City | Taipei |
| Period | 17/7/24 → 17/7/26 |
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Keywords
- Convolutional Neural Network
- Deep Neural Network
- Energy Efficiency
- FIFO
- Filter
- Line Buffer
- Weight
ASJC Scopus subject areas
- Engineering(all)
Cite this
Bit-width reduction and customized register for low cost convolutional neural network accelerator. / Choi, Kyungrak; Choi, Woong; Shin, Kyungho; Park, Jongsun.
ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., 2017. 8009164.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
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TY - GEN
T1 - Bit-width reduction and customized register for low cost convolutional neural network accelerator
AU - Choi, Kyungrak
AU - Choi, Woong
AU - Shin, Kyungho
AU - Park, Jongsun
PY - 2017/8/11
Y1 - 2017/8/11
N2 - This paper presents a low area and energy efficient hardware accelerator for the deep convolutional neural networks (CNNs). Based on the multiply-accumulate (MAC) based architecture, three design techniques are proposed to reduce the hardware cost of the convolutional computations. First, to reduce the computational bit-width of convolutions, an adaptive bit-width reduction scheme is proposed based on differential input method. The bit-width reduction approach can reduce the 37 % of operation bit-width with almost ignorable CNN accuracy degradation. Second, it has been found that adapting bi-directional filtering window in CNN accelerator can considerably reduce the energy for data movement with much smaller number of memory accesses. To expedite the bi-directional filtering operations, we also propose a bidirectional first-input-first-output (bi-FIFO). With SRAM bit-cell layout manner, the proposed bi-FIFO facilitates fast data re-distribution with area and energy efficiency. To verify the effectiveness of the proposed techniques, the AlexNet accelerator has been designed. The numerical results show that the proposed adaptive bit-width reduction scheme achieves 25.9% and 47.3% of area and energy savings, respectively. The bi-FIFO based accelerator also achieves 33 % improved processing time.
AB - This paper presents a low area and energy efficient hardware accelerator for the deep convolutional neural networks (CNNs). Based on the multiply-accumulate (MAC) based architecture, three design techniques are proposed to reduce the hardware cost of the convolutional computations. First, to reduce the computational bit-width of convolutions, an adaptive bit-width reduction scheme is proposed based on differential input method. The bit-width reduction approach can reduce the 37 % of operation bit-width with almost ignorable CNN accuracy degradation. Second, it has been found that adapting bi-directional filtering window in CNN accelerator can considerably reduce the energy for data movement with much smaller number of memory accesses. To expedite the bi-directional filtering operations, we also propose a bidirectional first-input-first-output (bi-FIFO). With SRAM bit-cell layout manner, the proposed bi-FIFO facilitates fast data re-distribution with area and energy efficiency. To verify the effectiveness of the proposed techniques, the AlexNet accelerator has been designed. The numerical results show that the proposed adaptive bit-width reduction scheme achieves 25.9% and 47.3% of area and energy savings, respectively. The bi-FIFO based accelerator also achieves 33 % improved processing time.
KW - Convolutional Neural Network
KW - Deep Neural Network
KW - Energy Efficiency
KW - FIFO
KW - Filter
KW - Line Buffer
KW - Weight
UR - http://www.scopus.com/inward/record.url?scp=85028582850&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85028582850&partnerID=8YFLogxK
U2 - 10.1109/ISLPED.2017.8009164
DO - 10.1109/ISLPED.2017.8009164
M3 - Conference contribution
BT - ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design
PB - Institute of Electrical and Electronics Engineers Inc.
ER -