Bit-width reduction and customized register for low cost convolutional neural network accelerator

Kyungrak Choi, Woong Choi, Kyungho Shin, Jongsun Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

This paper presents a low area and energy efficient hardware accelerator for the deep convolutional neural networks (CNNs). Based on the multiply-accumulate (MAC) based architecture, three design techniques are proposed to reduce the hardware cost of the convolutional computations. First, to reduce the computational bit-width of convolutions, an adaptive bit-width reduction scheme is proposed based on differential input method. The bit-width reduction approach can reduce the 37 % of operation bit-width with almost ignorable CNN accuracy degradation. Second, it has been found that adapting bi-directional filtering window in CNN accelerator can considerably reduce the energy for data movement with much smaller number of memory accesses. To expedite the bi-directional filtering operations, we also propose a bidirectional first-input-first-output (bi-FIFO). With SRAM bit-cell layout manner, the proposed bi-FIFO facilitates fast data re-distribution with area and energy efficiency. To verify the effectiveness of the proposed techniques, the AlexNet accelerator has been designed. The numerical results show that the proposed adaptive bit-width reduction scheme achieves 25.9% and 47.3% of area and energy savings, respectively. The bi-FIFO based accelerator also achieves 33 % improved processing time.

Original languageEnglish
Title of host publicationISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509060238
DOIs
Publication statusPublished - 2017 Aug 11
Event22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017 - Taipei, Taiwan, Province of China
Duration: 2017 Jul 242017 Jul 26

Other

Other22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017
CountryTaiwan, Province of China
CityTaipei
Period17/7/2417/7/26

Keywords

  • Convolutional Neural Network
  • Deep Neural Network
  • Energy Efficiency
  • FIFO
  • Filter
  • Line Buffer
  • Weight

ASJC Scopus subject areas

  • Engineering(all)

Fingerprint Dive into the research topics of 'Bit-width reduction and customized register for low cost convolutional neural network accelerator'. Together they form a unique fingerprint.

  • Cite this

    Choi, K., Choi, W., Shin, K., & Park, J. (2017). Bit-width reduction and customized register for low cost convolutional neural network accelerator. In ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design [8009164] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISLPED.2017.8009164