Bonding based channel transfer and low temperature process for monolithic 3D integration platform development

Rino Choi, Hyun Yong Yu, Hyungsub Kim, Han Youl Ryu, Hee Kyung Bae, Kevin Kinam Choi, Yong Won Cha, Changhwan Choi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We have studied low temperature processes for monolithic 3D integration platform development including hydrogen/helium ion implantation-based wafer cleavage & bonding (< 450°C), low temperature (< 550°C) in-situ doped S/D selective SiGe epi process, low temperature (< 200°C) gate stack on the chemical-mechanical polished (CMP) wafer, and green-lased annealing. These unit technologies can be adopted to achieve 3D integration platform technology for the high performance and low power applications.

Original languageEnglish
Title of host publication2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509043903
DOIs
Publication statusPublished - 2017 Jan 3
Event2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016 - Burlingame, United States
Duration: 2016 Oct 102016 Oct 13

Publication series

Name2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016

Other

Other2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016
CountryUnited States
CityBurlingame
Period16/10/1016/10/13

Keywords

  • Epitaxial Growth
  • Gate Stack
  • Laser Annealing
  • Low Temperature Bonding
  • Monolithic 3D

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Instrumentation

Fingerprint Dive into the research topics of 'Bonding based channel transfer and low temperature process for monolithic 3D integration platform development'. Together they form a unique fingerprint.

Cite this