@inproceedings{2afbb1c2b3c44d3d8b51cfb31ef20473,
title = "Bonding based channel transfer and low temperature process for monolithic 3D integration platform development",
abstract = "We have studied low temperature processes for monolithic 3D integration platform development including hydrogen/helium ion implantation-based wafer cleavage & bonding (< 450°C), low temperature (< 550°C) in-situ doped S/D selective SiGe epi process, low temperature (< 200°C) gate stack on the chemical-mechanical polished (CMP) wafer, and green-lased annealing. These unit technologies can be adopted to achieve 3D integration platform technology for the high performance and low power applications.",
keywords = "Epitaxial Growth, Gate Stack, Laser Annealing, Low Temperature Bonding, Monolithic 3D",
author = "Rino Choi and Yu, {Hyun Yong} and Hyungsub Kim and Ryu, {Han Youl} and Bae, {Hee Kyung} and Choi, {Kevin Kinam} and Cha, {Yong Won} and Changhwan Choi",
note = "Funding Information: This research was supported by the Nano Material Technology Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (NRF-2015M3A7B7045490). Publisher Copyright: {\textcopyright} 2016 IEEE.; 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016 ; Conference date: 10-10-2016 Through 13-10-2016",
year = "2017",
month = jan,
day = "3",
doi = "10.1109/S3S.2016.7804407",
language = "English",
series = "2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016",
}