Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs

Taeweon Suh; Daehyun Kim; Hsien Hsin S. Lee

doi:10.1145/1065579.1065725

Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs

Taeweon Suh, Daehyun Kim, Hsien Hsin S. Lee

Research output: Contribution to journal › Conference article › peer-review

4 Citations (Scopus)

Abstract

We propose two novel integration techniques - bypass and bookkeeping - in the memory controller to address the cache coherence compatibility issue of a non-shared bus heterogeneous MPSoC. The bypass approach is an inexpensive and efficient solution for computation-bound applications while the bookkeeping approach eliminating unnecessary forwarding traffic offers an alternative for bandwidth-limited applications. Our RTOS kernel simulations show up to 6.65x speedup over the conventional software solution.

Original language	English
Article number	34.1
Pages (from-to)	553-558
Number of pages	6
Journal	Proceedings - Design Automation Conference
DOIs	https://doi.org/10.1145/1065579.1065725
Publication status	Published - 2005
Externally published	Yes
Event	42nd Design Automation Conference, DAC 2005 - Anaheim, CA, United States Duration: 2005 Jun 13 → 2005 Jun 17

Keywords

Cache coherence
Heterogeneous MPSoC
Inter-processor communication
Real-time and embedded systems

ASJC Scopus subject areas

Hardware and Architecture
Control and Systems Engineering

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10.1145/1065579.1065725

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AU - Kim, Daehyun

AU - Lee, Hsien Hsin S.

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Y1 - 2005

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AB - We propose two novel integration techniques - bypass and bookkeeping - in the memory controller to address the cache coherence compatibility issue of a non-shared bus heterogeneous MPSoC. The bypass approach is an inexpensive and efficient solution for computation-bound applications while the bookkeeping approach eliminating unnecessary forwarding traffic offers an alternative for bandwidth-limited applications. Our RTOS kernel simulations show up to 6.65x speedup over the conventional software solution.

KW - Cache coherence

KW - Heterogeneous MPSoC

KW - Inter-processor communication

KW - Real-time and embedded systems

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T2 - 42nd Design Automation Conference, DAC 2005

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ER -

Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs

Abstract

Keywords

ASJC Scopus subject areas

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