Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs

Taeweon Suh, Daehyun Kim, Hsien Hsin S. Lee

Research output: Contribution to journalConference articlepeer-review

4 Citations (Scopus)


We propose two novel integration techniques - bypass and bookkeeping - in the memory controller to address the cache coherence compatibility issue of a non-shared bus heterogeneous MPSoC. The bypass approach is an inexpensive and efficient solution for computation-bound applications while the bookkeeping approach eliminating unnecessary forwarding traffic offers an alternative for bandwidth-limited applications. Our RTOS kernel simulations show up to 6.65x speedup over the conventional software solution.

Original languageEnglish
Article number34.1
Pages (from-to)553-558
Number of pages6
JournalProceedings - Design Automation Conference
Publication statusPublished - 2005
Externally publishedYes
Event42nd Design Automation Conference, DAC 2005 - Anaheim, CA, United States
Duration: 2005 Jun 132005 Jun 17


  • Cache coherence
  • Heterogeneous MPSoC
  • Inter-processor communication
  • Real-time and embedded systems

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering


Dive into the research topics of 'Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs'. Together they form a unique fingerprint.

Cite this