Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs

Taeweon Suh, Daehyun Kim, Hsien Hsin S Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

We propose two novel integration techniques - bypass and bookkeeping - in the memory controller to address the cache coherence compatibility issue of a non-shared bus heterogeneous MPSoC. The bypass approach is an inexpensive and efficient solution for computation-bound applications while the bookkeeping approach eliminating unnecessary forwarding traffic offers an alternative for bandwidth-limited applications. Our RTOS kernel simulations show up to 6.65x speedup over the conventional software solution.

Original languageEnglish
Title of host publicationProceedings - Design Automation Conference
Pages553-558
Number of pages6
Publication statusPublished - 2005
Externally publishedYes
Event42nd Design Automation Conference, DAC 2005 - Anaheim, CA, United States
Duration: 2005 Jun 132005 Jun 17

Other

Other42nd Design Automation Conference, DAC 2005
CountryUnited States
CityAnaheim, CA
Period05/6/1305/6/17

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Keywords

  • Cache coherence
  • Heterogeneous MPSoC
  • Inter-processor communication
  • Real-time and embedded systems

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

Cite this

Suh, T., Kim, D., & Lee, H. H. S. (2005). Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs. In Proceedings - Design Automation Conference (pp. 553-558). [34.1]