Centaur: a hybrid network-on-chip architecture utilizing micro-network fusion

Junghee Lee, Chrysostomos Nicopoulos, Hyung Gyu Lee, Jongman Kim

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

The escalating proliferation of multicore chips has accentuated the criticality of the on-chip network. Packet-based networks-on-chip (NoC) have emerged as the de facto interconnect of future chip multi-processors (CMP). On-chip traffic comprises a mixture of data and control messages from the cache coherence protocol. Given the latency-criticality of control messages, in this paper we aim to optimize their delivery times. Instead of treating the on-chip router as a monolithic component, we advocate the introduction of an ultra-low-latency ring-inspired (i.e., utilizing ring primitive building blocks) support micro-network that is optimized for control messages. This $$\upmu $$μNoC is fused with a throughput-driven conventional NoC router to form a hybrid architecture, called Centaur, which maintains separate data paths and control logic for the two fused networks. Full-system simulation results from a 64-core CMP indicate that the proposed fused Centaur router improves overall system performance by up to 26 %, as compared to a state-of-the-art router implementation. Furthermore, hardware synthesis results using commercial 65 nm libraries indicate that Centaur’s area and power overheads are 9 and 3 %, respectively, as compared to a baseline router design. More importantly, the new design does not affect the router’s critical path.

Original languageEnglish
Pages (from-to)121-139
Number of pages19
JournalDesign Automation for Embedded Systems
Volume18
Issue number3-4
DOIs
Publication statusPublished - 2014 Sep 20
Externally publishedYes

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Routers
Fusion reactions
Network-on-chip
Throughput
Hardware

Keywords

  • Interconnection networks
  • Networks-on-chip
  • Segregated/separated networks

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture

Cite this

Centaur : a hybrid network-on-chip architecture utilizing micro-network fusion. / Lee, Junghee; Nicopoulos, Chrysostomos; Lee, Hyung Gyu; Kim, Jongman.

In: Design Automation for Embedded Systems, Vol. 18, No. 3-4, 20.09.2014, p. 121-139.

Research output: Contribution to journalArticle

Lee, Junghee ; Nicopoulos, Chrysostomos ; Lee, Hyung Gyu ; Kim, Jongman. / Centaur : a hybrid network-on-chip architecture utilizing micro-network fusion. In: Design Automation for Embedded Systems. 2014 ; Vol. 18, No. 3-4. pp. 121-139.
@article{d799fe94653b4df48e4880a25ecbd728,
title = "Centaur: a hybrid network-on-chip architecture utilizing micro-network fusion",
abstract = "The escalating proliferation of multicore chips has accentuated the criticality of the on-chip network. Packet-based networks-on-chip (NoC) have emerged as the de facto interconnect of future chip multi-processors (CMP). On-chip traffic comprises a mixture of data and control messages from the cache coherence protocol. Given the latency-criticality of control messages, in this paper we aim to optimize their delivery times. Instead of treating the on-chip router as a monolithic component, we advocate the introduction of an ultra-low-latency ring-inspired (i.e., utilizing ring primitive building blocks) support micro-network that is optimized for control messages. This $$\upmu $$μNoC is fused with a throughput-driven conventional NoC router to form a hybrid architecture, called Centaur, which maintains separate data paths and control logic for the two fused networks. Full-system simulation results from a 64-core CMP indicate that the proposed fused Centaur router improves overall system performance by up to 26 {\%}, as compared to a state-of-the-art router implementation. Furthermore, hardware synthesis results using commercial 65 nm libraries indicate that Centaur’s area and power overheads are 9 and 3 {\%}, respectively, as compared to a baseline router design. More importantly, the new design does not affect the router’s critical path.",
keywords = "Interconnection networks, Networks-on-chip, Segregated/separated networks",
author = "Junghee Lee and Chrysostomos Nicopoulos and Lee, {Hyung Gyu} and Jongman Kim",
year = "2014",
month = "9",
day = "20",
doi = "10.1007/s10617-014-9131-z",
language = "English",
volume = "18",
pages = "121--139",
journal = "Design Automation for Embedded Systems",
issn = "0929-5585",
publisher = "Springer Netherlands",
number = "3-4",

}

TY - JOUR

T1 - Centaur

T2 - a hybrid network-on-chip architecture utilizing micro-network fusion

AU - Lee, Junghee

AU - Nicopoulos, Chrysostomos

AU - Lee, Hyung Gyu

AU - Kim, Jongman

PY - 2014/9/20

Y1 - 2014/9/20

N2 - The escalating proliferation of multicore chips has accentuated the criticality of the on-chip network. Packet-based networks-on-chip (NoC) have emerged as the de facto interconnect of future chip multi-processors (CMP). On-chip traffic comprises a mixture of data and control messages from the cache coherence protocol. Given the latency-criticality of control messages, in this paper we aim to optimize their delivery times. Instead of treating the on-chip router as a monolithic component, we advocate the introduction of an ultra-low-latency ring-inspired (i.e., utilizing ring primitive building blocks) support micro-network that is optimized for control messages. This $$\upmu $$μNoC is fused with a throughput-driven conventional NoC router to form a hybrid architecture, called Centaur, which maintains separate data paths and control logic for the two fused networks. Full-system simulation results from a 64-core CMP indicate that the proposed fused Centaur router improves overall system performance by up to 26 %, as compared to a state-of-the-art router implementation. Furthermore, hardware synthesis results using commercial 65 nm libraries indicate that Centaur’s area and power overheads are 9 and 3 %, respectively, as compared to a baseline router design. More importantly, the new design does not affect the router’s critical path.

AB - The escalating proliferation of multicore chips has accentuated the criticality of the on-chip network. Packet-based networks-on-chip (NoC) have emerged as the de facto interconnect of future chip multi-processors (CMP). On-chip traffic comprises a mixture of data and control messages from the cache coherence protocol. Given the latency-criticality of control messages, in this paper we aim to optimize their delivery times. Instead of treating the on-chip router as a monolithic component, we advocate the introduction of an ultra-low-latency ring-inspired (i.e., utilizing ring primitive building blocks) support micro-network that is optimized for control messages. This $$\upmu $$μNoC is fused with a throughput-driven conventional NoC router to form a hybrid architecture, called Centaur, which maintains separate data paths and control logic for the two fused networks. Full-system simulation results from a 64-core CMP indicate that the proposed fused Centaur router improves overall system performance by up to 26 %, as compared to a state-of-the-art router implementation. Furthermore, hardware synthesis results using commercial 65 nm libraries indicate that Centaur’s area and power overheads are 9 and 3 %, respectively, as compared to a baseline router design. More importantly, the new design does not affect the router’s critical path.

KW - Interconnection networks

KW - Networks-on-chip

KW - Segregated/separated networks

UR - http://www.scopus.com/inward/record.url?scp=84931570345&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84931570345&partnerID=8YFLogxK

U2 - 10.1007/s10617-014-9131-z

DO - 10.1007/s10617-014-9131-z

M3 - Article

AN - SCOPUS:84931570345

VL - 18

SP - 121

EP - 139

JO - Design Automation for Embedded Systems

JF - Design Automation for Embedded Systems

SN - 0929-5585

IS - 3-4

ER -