Abstract
In this study, we investigate the influence of an overlap between the gate and source/drain regions of silicon nanowire (SiNW) CMOS (complementary metal-oxide-semiconductor) inverter on bendable plastic substrates and describe their electrical characteristics. The combination of n-channel silicon nanowire field-effect transistor (n-SiNWFET) and p-channel silicon nanowire field-effect transistor (p-SiNWFET) operates as an inverter logic gate. The gains with a drain voltage (Vdd) of 1 V are 3.07 and 1.21 for overlapped device and non-overlapped device, respectively. The superior electrical characteristics of each of the SiNW transistors including steep subthreshold slopes and the high Ion/Ioff ratios are major factors that enable the excellent operation of the logic gate.
| Original language | English |
|---|---|
| Pages (from-to) | 1494-1498 |
| Number of pages | 5 |
| Journal | Transactions of the Korean Institute of Electrical Engineers |
| Volume | 66 |
| Issue number | 10 |
| DOIs | |
| Publication status | Published - 2017 Jan 1 |
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Keywords
- Bendable electronics
- CMOS inverter
- Field effect transistor
- Gate overlap
- Silicon nanowire
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
Characteristics of nanowire CMOS inverter with gate overlap. / Yoo, Jeuk; Kim, Yoonjoong; Lim, Doohyeok; Kim, Sangsig.
In: Transactions of the Korean Institute of Electrical Engineers, Vol. 66, No. 10, 01.01.2017, p. 1494-1498.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Characteristics of nanowire CMOS inverter with gate overlap
AU - Yoo, Jeuk
AU - Kim, Yoonjoong
AU - Lim, Doohyeok
AU - Kim, Sangsig
PY - 2017/1/1
Y1 - 2017/1/1
N2 - In this study, we investigate the influence of an overlap between the gate and source/drain regions of silicon nanowire (SiNW) CMOS (complementary metal-oxide-semiconductor) inverter on bendable plastic substrates and describe their electrical characteristics. The combination of n-channel silicon nanowire field-effect transistor (n-SiNWFET) and p-channel silicon nanowire field-effect transistor (p-SiNWFET) operates as an inverter logic gate. The gains with a drain voltage (Vdd) of 1 V are 3.07 and 1.21 for overlapped device and non-overlapped device, respectively. The superior electrical characteristics of each of the SiNW transistors including steep subthreshold slopes and the high Ion/Ioff ratios are major factors that enable the excellent operation of the logic gate.
AB - In this study, we investigate the influence of an overlap between the gate and source/drain regions of silicon nanowire (SiNW) CMOS (complementary metal-oxide-semiconductor) inverter on bendable plastic substrates and describe their electrical characteristics. The combination of n-channel silicon nanowire field-effect transistor (n-SiNWFET) and p-channel silicon nanowire field-effect transistor (p-SiNWFET) operates as an inverter logic gate. The gains with a drain voltage (Vdd) of 1 V are 3.07 and 1.21 for overlapped device and non-overlapped device, respectively. The superior electrical characteristics of each of the SiNW transistors including steep subthreshold slopes and the high Ion/Ioff ratios are major factors that enable the excellent operation of the logic gate.
KW - Bendable electronics
KW - CMOS inverter
KW - Field effect transistor
KW - Gate overlap
KW - Silicon nanowire
UR - http://www.scopus.com/inward/record.url?scp=85040173382&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85040173382&partnerID=8YFLogxK
U2 - 10.5370/KIEE.2017.66.10.1494
DO - 10.5370/KIEE.2017.66.10.1494
M3 - Article
AN - SCOPUS:85040173382
VL - 66
SP - 1494
EP - 1498
JO - Transactions of the Korean Institute of Electrical Engineers
JF - Transactions of the Korean Institute of Electrical Engineers
SN - 1975-8359
IS - 10
ER -