Characteristics of nanowire CMOS inverter with gate overlap

Jeuk Yoo; Yoonjoong Kim; Doohyeok Lim; Sangsig Kim

doi:10.5370/KIEE.2017.66.10.1494

Characteristics of nanowire CMOS inverter with gate overlap

Jeuk Yoo, Yoonjoong Kim, Doohyeok Lim, Sangsig Kim

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

In this study, we investigate the influence of an overlap between the gate and source/drain regions of silicon nanowire (SiNW) CMOS (complementary metal-oxide-semiconductor) inverter on bendable plastic substrates and describe their electrical characteristics. The combination of n-channel silicon nanowire field-effect transistor (n-SiNWFET) and p-channel silicon nanowire field-effect transistor (p-SiNWFET) operates as an inverter logic gate. The gains with a drain voltage (Vdd) of 1 V are 3.07 and 1.21 for overlapped device and non-overlapped device, respectively. The superior electrical characteristics of each of the SiNW transistors including steep subthreshold slopes and the high Ion/Ioff ratios are major factors that enable the excellent operation of the logic gate.

Original language	English
Pages (from-to)	1494-1498
Number of pages	5
Journal	Transactions of the Korean Institute of Electrical Engineers
Volume	66
Issue number	10
DOIs	https://doi.org/10.5370/KIEE.2017.66.10.1494
Publication status	Published - 2017 Jan 1

Keywords

Bendable electronics
CMOS inverter
Field effect transistor
Gate overlap
Silicon nanowire

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.5370/KIEE.2017.66.10.1494

Cite this

@article{6511c50fc8ea45caa1750b200368738d,

title = "Characteristics of nanowire CMOS inverter with gate overlap",

abstract = "In this study, we investigate the influence of an overlap between the gate and source/drain regions of silicon nanowire (SiNW) CMOS (complementary metal-oxide-semiconductor) inverter on bendable plastic substrates and describe their electrical characteristics. The combination of n-channel silicon nanowire field-effect transistor (n-SiNWFET) and p-channel silicon nanowire field-effect transistor (p-SiNWFET) operates as an inverter logic gate. The gains with a drain voltage (Vdd) of 1 V are 3.07 and 1.21 for overlapped device and non-overlapped device, respectively. The superior electrical characteristics of each of the SiNW transistors including steep subthreshold slopes and the high Ion/Ioff ratios are major factors that enable the excellent operation of the logic gate.",

keywords = "Bendable electronics, CMOS inverter, Field effect transistor, Gate overlap, Silicon nanowire",

author = "Jeuk Yoo and Yoonjoong Kim and Doohyeok Lim and Sangsig Kim",

year = "2017",

month = jan,

day = "1",

doi = "10.5370/KIEE.2017.66.10.1494",

language = "English",

volume = "66",

pages = "1494--1498",

journal = "Transactions of the Korean Institute of Electrical Engineers",

issn = "1975-8359",

publisher = "Korean Institute of Electrical Engineers",

number = "10",

}

TY - JOUR

T1 - Characteristics of nanowire CMOS inverter with gate overlap

AU - Yoo, Jeuk

AU - Kim, Yoonjoong

AU - Lim, Doohyeok

AU - Kim, Sangsig

PY - 2017/1/1

Y1 - 2017/1/1

N2 - In this study, we investigate the influence of an overlap between the gate and source/drain regions of silicon nanowire (SiNW) CMOS (complementary metal-oxide-semiconductor) inverter on bendable plastic substrates and describe their electrical characteristics. The combination of n-channel silicon nanowire field-effect transistor (n-SiNWFET) and p-channel silicon nanowire field-effect transistor (p-SiNWFET) operates as an inverter logic gate. The gains with a drain voltage (Vdd) of 1 V are 3.07 and 1.21 for overlapped device and non-overlapped device, respectively. The superior electrical characteristics of each of the SiNW transistors including steep subthreshold slopes and the high Ion/Ioff ratios are major factors that enable the excellent operation of the logic gate.

AB - In this study, we investigate the influence of an overlap between the gate and source/drain regions of silicon nanowire (SiNW) CMOS (complementary metal-oxide-semiconductor) inverter on bendable plastic substrates and describe their electrical characteristics. The combination of n-channel silicon nanowire field-effect transistor (n-SiNWFET) and p-channel silicon nanowire field-effect transistor (p-SiNWFET) operates as an inverter logic gate. The gains with a drain voltage (Vdd) of 1 V are 3.07 and 1.21 for overlapped device and non-overlapped device, respectively. The superior electrical characteristics of each of the SiNW transistors including steep subthreshold slopes and the high Ion/Ioff ratios are major factors that enable the excellent operation of the logic gate.

KW - Bendable electronics

KW - CMOS inverter

KW - Field effect transistor

KW - Gate overlap

KW - Silicon nanowire

UR - http://www.scopus.com/inward/record.url?scp=85040173382&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85040173382&partnerID=8YFLogxK

U2 - 10.5370/KIEE.2017.66.10.1494

DO - 10.5370/KIEE.2017.66.10.1494

M3 - Article

AN - SCOPUS:85040173382

VL - 66

SP - 1494

EP - 1498

JO - Transactions of the Korean Institute of Electrical Engineers

JF - Transactions of the Korean Institute of Electrical Engineers

SN - 1975-8359

IS - 10

ER -

Characteristics of nanowire CMOS inverter with gate overlap

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this