Abstract
In this study, we investigate the influence of an overlap between the gate and source/drain regions of silicon nanowire (SiNW) CMOS (complementary metal-oxide-semiconductor) inverter on bendable plastic substrates and describe their electrical characteristics. The combination of n-channel silicon nanowire field-effect transistor (n-SiNWFET) and p-channel silicon nanowire field-effect transistor (p-SiNWFET) operates as an inverter logic gate. The gains with a drain voltage (Vdd) of 1 V are 3.07 and 1.21 for overlapped device and non-overlapped device, respectively. The superior electrical characteristics of each of the SiNW transistors including steep subthreshold slopes and the high Ion/Ioff ratios are major factors that enable the excellent operation of the logic gate.
Original language | English |
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Pages (from-to) | 1494-1498 |
Number of pages | 5 |
Journal | Transactions of the Korean Institute of Electrical Engineers |
Volume | 66 |
Issue number | 10 |
DOIs | |
Publication status | Published - 2017 Jan 1 |
Keywords
- Bendable electronics
- CMOS inverter
- Field effect transistor
- Gate overlap
- Silicon nanowire
ASJC Scopus subject areas
- Electrical and Electronic Engineering