TY - GEN
T1 - Charge-Recycling based Redundant Write Prevention Technique for Low Power SOT-MRAM
AU - Kang, Gyuseong
AU - Jang, Yunho
AU - Park, Jongsun
N1 - Funding Information:
This work was supported by the National Research Foundation of Korea grant funded by the Korea government (NRF-2016 R1A2B4015329 and NRF-2015M3D1A1070465), and the Information Technology Research and Development Program of Korea Evaluation Institute of Industrial Technology [10052716, Design technology development of ultralow voltage operating circuit and IP for smart sensor SoC]
Publisher Copyright:
© 2018 IEEE.
PY - 2018/4/26
Y1 - 2018/4/26
N2 - While the spin transfer torque magnetic memory (STT-MRAM) suffers from its shortcomings such as high write power, slow write operation and reliability issues, spin orbit torque magnetic random access memory (SOT-MRAM) can offer relatively faster write operation with low power based on giant spin hall effect. Although SOT-MRAM provides low power write operation, to meet the power level of current embedded memories, significant reduction of write power is highly required. In this paper, we present a low power write technique for SOT-MRAM. In order to prevent redundant write operation, read-compare-write operation is adopted. As a result, only the SOT cells having different data are written, and write power is saved in the cells with the same data. For further optimization, bitline switching scheme is used to reduce bitline and source line swing in write operation. The negative bitline scheme is also exploited by re-cycling the charge from read operation to increase write current. Simulation results using 65nm CMOS technology show that up to 40.1 % of write energy can be saved compared to the conventional unnecessary write avoidance approach.
AB - While the spin transfer torque magnetic memory (STT-MRAM) suffers from its shortcomings such as high write power, slow write operation and reliability issues, spin orbit torque magnetic random access memory (SOT-MRAM) can offer relatively faster write operation with low power based on giant spin hall effect. Although SOT-MRAM provides low power write operation, to meet the power level of current embedded memories, significant reduction of write power is highly required. In this paper, we present a low power write technique for SOT-MRAM. In order to prevent redundant write operation, read-compare-write operation is adopted. As a result, only the SOT cells having different data are written, and write power is saved in the cells with the same data. For further optimization, bitline switching scheme is used to reduce bitline and source line swing in write operation. The negative bitline scheme is also exploited by re-cycling the charge from read operation to increase write current. Simulation results using 65nm CMOS technology show that up to 40.1 % of write energy can be saved compared to the conventional unnecessary write avoidance approach.
KW - SOT-MRAM
KW - spin-orbit torque (SOT)
KW - write power reduction
UR - http://www.scopus.com/inward/record.url?scp=85057114429&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2018.8351277
DO - 10.1109/ISCAS.2018.8351277
M3 - Conference contribution
AN - SCOPUS:85057114429
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
Y2 - 27 May 2018 through 30 May 2018
ER -