Charge-sharing-problem reduced split-path domino logic

Seok Soo Yoon, Seok Ryong Yoon, Seon Wook Kim, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In this paper, we describe split-path domino (SP domino) logic which is capable of high speed due to the magnitude of the charge sharing problem being halved. SP domino logic splits the NMOS stacked transistors used for logic evaluation, in order to reduce charge sharing problem, which has become one of the most critical noise problems in VDSM technology. Furthermore, SP domino logic needs no signal ordering. Dual Vt assignment methodology for SP domino logic was also proposed, in order to provide improved performance with low power consumption overhead. Our experimental results, with several logic gates using 0.18um CMOS technology, showed that the proposed logic provides an improvement in performance of up to 17% compared to the textbook domino circuit, under the same noisy conditions. Hence, SP domino logic is a good candidate for high-speed low-voltage operation in a very noisy environment.

Original languageEnglish
Title of host publicationProceedings of the IEEE International Conference on VLSI Design
Pages201-205
Number of pages5
Volume17
Publication statusPublished - 2004
EventProceedings - 17th International Conference on VLSI Design, Concurrently with the 3rd International Conference on Embedded Systems Design - Mumbai, India
Duration: 2004 Jan 52004 Jan 9

Other

OtherProceedings - 17th International Conference on VLSI Design, Concurrently with the 3rd International Conference on Embedded Systems Design
CountryIndia
CityMumbai
Period04/1/504/1/9

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Yoon, S. S., Yoon, S. R., Kim, S. W., & Kim, C. (2004). Charge-sharing-problem reduced split-path domino logic. In Proceedings of the IEEE International Conference on VLSI Design (Vol. 17, pp. 201-205)