Charge-trap flash memory devices fabricated with nano-scale patterns on the Si 3N 4 trapping layer

Ho Myoung An, Kyong Heon Kim, Hee Dong Kim, Won Ju Cho, Tae Geun Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

We proposed a novel CTF memory structure with surface patterned Si 3N 4 trap layers, in order to enhance the memory window and the performance for ultra-high density CTF devices. Due to the enlargement of surface memory-trap densities, the CTF devices with nano-scale surface patterns on the Si 3N 4 trap layer by NSL showed increased memory windows and improved program properties. In addition, the reasonable reliability, including data retention of 10 years and endurance of 10 4 P/E cycles, was obtained.

Original languageEnglish
Title of host publication2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012
DOIs
Publication statusPublished - 2012
Event2012 17th IEEE Silicon Nanoelectronics Workshop, SNW 2012 - Honolulu, HI, United States
Duration: 2012 Jun 102012 Jun 11

Publication series

Name2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012

Other

Other2012 17th IEEE Silicon Nanoelectronics Workshop, SNW 2012
CountryUnited States
CityHonolulu, HI
Period12/6/1012/6/11

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    An, H. M., Kim, K. H., Kim, H. D., Cho, W. J., & Kim, T. G. (2012). Charge-trap flash memory devices fabricated with nano-scale patterns on the Si 3N 4 trapping layer. In 2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012 [6243350] (2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012). https://doi.org/10.1109/SNW.2012.6243350