Circuit design techniques for multimedia wireline communications

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents several circuit design techniques for multimedia wireline interfaces. A 7.5 Gb/s transceiver with pre-emphasis and bandwidth (BW)-shifting techniques are introduced. By applying dynamic calibration technique for pre-emphasis, the measured transmitter eye-opening is improved by 24 %. BW shifting clock generator achieves the jitter reduction of 43%. In addition, a wide input range comparator for 11.2 Gb/s low-voltage-differential-swing (LVDS) multi-channel receiver is also introduced. The comparator achieves 81.9 % of the received data RMS jitter reduction for the LVDS receiver.

Original languageEnglish
Title of host publicationProceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479984831
DOIs
Publication statusPublished - 2016 Jul 19
Event11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China
Duration: 2015 Nov 32015 Nov 6

Other

Other11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
CountryChina
CityChengdu
Period15/11/315/11/6

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Kim, C. (2016). Circuit design techniques for multimedia wireline communications. In Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015 [7516917] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASICON.2015.7516917