In this paper, we study a hardware-supported, compiler-directed (HSCD) cache coherence scheme, which can be implemented on a large-scale multiprocessor using off-the-shelf microprocessors, such as the Cray T3D. It can be adapted to various cache organizations, including multi-word cache lines and byte-addressable architectures. Several system related issues, including critical sections, inter-thread communication, and task migration have also been addressed. The cost of the required hardware support is small and proportional to the cache size. The necessary compiler algorithms, including intra- and interprocedural array data-flow analysis, have been implemented on the Polaris compiler . From our simulation study using the Perfect Club benchmarks, we found that, in spite of the conservative analysis made by the compiler, the performance of the proposed HSCD scheme can be comparable to that of a full-map hardware directory scheme. With its comparable performance and reduced hardware cost, the scheme can be a viable alternative for large-scale multiprocessors, such as the Cray T3D, that rely on users to maintain data coherence.
|Number of pages||12|
|Journal||Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA|
|Publication status||Published - 1996|
|Event||Proceedings of the 1996 23rd Annual International Symposium on Computer Architecture - Philadelphia, PA, USA|
Duration: 1996 May 22 → 1996 May 24
ASJC Scopus subject areas
- Hardware and Architecture