Compiler techniques for energy saving in instruction caches of speculative parallel microarchitectures

Seon Wook Kim, R. Eigenmann

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We present a new software scheme, called compiler-assisted I-cache prediction (CIP) for energy reduction in instruction caches. With the help of compiler-supplied information, the processor is able to turn off substantial portions of the I-cache. The necessary cache sets are only turned on during the execution of individual code sections. The CIP scheme is based on the processor's ability to predict code sections that are about to execute and on the compiler's ability to precisely inform the hardware about the size of these code sections. Our techniques grew out of work with optimizing compilers for speculative parallel microarchitectures. The use of this target machine class is further motivated by the fact that speculative processors have the potential to overcome limitations in the compiler parallelization of many applications, especially non-numerical programs. Speculative microarchitectures are also among the most promising emerging architectures that can take advantage of the ever-increasing levels of chip integration. We will show that our new techniques can lead up to 90% I-cache energy savings in general-purpose applications without significant execution overhead. We believe that this is a substantial step towards the goal of making such chips integral parts of mobile computing devices, such as laptops, palm tops, and cellular phones.

Original languageEnglish
Title of host publicationProceedings of the International Conference on Parallel Processing
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages77-84
Number of pages8
Volume2000-January
ISBN (Print)0769507689
DOIs
Publication statusPublished - 2000
Externally publishedYes
EventInternational Conference on Parallel Processing, ICPP 2000 - Toronto, Canada
Duration: 2000 Aug 212000 Aug 24

Other

OtherInternational Conference on Parallel Processing, ICPP 2000
CountryCanada
CityToronto
Period00/8/2100/8/24

Fingerprint

Energy Saving
Compiler
Cache
Energy conservation
Mobile computing
Hardware
Chip
Optimizing Compilers
Prediction
Mobile Computing
Parallelization
Predict
Target
Software
Necessary
Energy

Keywords

  • Cellular phones
  • Computer aided instruction
  • Concurrent computing
  • Government
  • Hardware
  • Microarchitecture
  • Mobile computing
  • Portable computers
  • Power engineering and energy
  • Program processors

ASJC Scopus subject areas

  • Software
  • Mathematics(all)
  • Hardware and Architecture

Cite this

Kim, S. W., & Eigenmann, R. (2000). Compiler techniques for energy saving in instruction caches of speculative parallel microarchitectures. In Proceedings of the International Conference on Parallel Processing (Vol. 2000-January, pp. 77-84). [876081] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICPP.2000.876081

Compiler techniques for energy saving in instruction caches of speculative parallel microarchitectures. / Kim, Seon Wook; Eigenmann, R.

Proceedings of the International Conference on Parallel Processing. Vol. 2000-January Institute of Electrical and Electronics Engineers Inc., 2000. p. 77-84 876081.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kim, SW & Eigenmann, R 2000, Compiler techniques for energy saving in instruction caches of speculative parallel microarchitectures. in Proceedings of the International Conference on Parallel Processing. vol. 2000-January, 876081, Institute of Electrical and Electronics Engineers Inc., pp. 77-84, International Conference on Parallel Processing, ICPP 2000, Toronto, Canada, 00/8/21. https://doi.org/10.1109/ICPP.2000.876081
Kim SW, Eigenmann R. Compiler techniques for energy saving in instruction caches of speculative parallel microarchitectures. In Proceedings of the International Conference on Parallel Processing. Vol. 2000-January. Institute of Electrical and Electronics Engineers Inc. 2000. p. 77-84. 876081 https://doi.org/10.1109/ICPP.2000.876081
Kim, Seon Wook ; Eigenmann, R. / Compiler techniques for energy saving in instruction caches of speculative parallel microarchitectures. Proceedings of the International Conference on Parallel Processing. Vol. 2000-January Institute of Electrical and Electronics Engineers Inc., 2000. pp. 77-84
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