TY - GEN
T1 - Compiling for speculative architectures
AU - Kim, Seon Wook
AU - Eigenmann, Rudolf
N1 - Publisher Copyright:
© Springer-Verlag Berlin Heidelberg 2000.
Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2000
Y1 - 2000
N2 - The traditional target machine of a parallelizing compiler can execute code sections either serially or in parallel. In contrast, tar- geting the generated code to a speculative parallel processor allows the compiler to recognize parallelism to the best of its abilities and leave other optimization decisions up to the processor's runtime detection me- chanisms. In this paper we show that simple improvements of the com- piler's speculative task selection method can already lead to signi_cant (up to 55%) improvement in speedup over that of a simple code genera- tor for a Multiscalar architecture. For an even more improved software/hardware cooperation we propose an interface that allows the compiler to inform the processor about fully parallel, serial, and speculative code sections as well as attributes of program variables. We have evaluated the degrees of parallelism that such a co-design can realistically exploit.
AB - The traditional target machine of a parallelizing compiler can execute code sections either serially or in parallel. In contrast, tar- geting the generated code to a speculative parallel processor allows the compiler to recognize parallelism to the best of its abilities and leave other optimization decisions up to the processor's runtime detection me- chanisms. In this paper we show that simple improvements of the com- piler's speculative task selection method can already lead to signi_cant (up to 55%) improvement in speedup over that of a simple code genera- tor for a Multiscalar architecture. For an even more improved software/hardware cooperation we propose an interface that allows the compiler to inform the processor about fully parallel, serial, and speculative code sections as well as attributes of program variables. We have evaluated the degrees of parallelism that such a co-design can realistically exploit.
UR - http://www.scopus.com/inward/record.url?scp=84948965894&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84948965894&partnerID=8YFLogxK
U2 - 10.1007/3-540-44905-1_32
DO - 10.1007/3-540-44905-1_32
M3 - Conference contribution
AN - SCOPUS:84948965894
SN - 9783540678588
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 464
EP - 467
BT - Languages and Compilers for Parallel Computing - 12th International Workshop, LCPC 1999, Proceedings
A2 - Carter, Larry
A2 - Ferrante, Jeanne
PB - Springer Verlag
T2 - 12th International Workshop on Languages and Compilers for Parallel Computing, LCPC 1999
Y2 - 4 August 1999 through 6 August 1999
ER -