Abstract
The traditional target machine of a parallelizing compiler can execute code sections either serially or in parallel. In contrast, tar- geting the generated code to a speculative parallel processor allows the compiler to recognize parallelism to the best of its abilities and leave other optimization decisions up to the processor's runtime detection me- chanisms. In this paper we show that simple improvements of the com- piler's speculative task selection method can already lead to signi_cant (up to 55%) improvement in speedup over that of a simple code genera- tor for a Multiscalar architecture. For an even more improved software/hardware cooperation we propose an interface that allows the compiler to inform the processor about fully parallel, serial, and speculative code sections as well as attributes of program variables. We have evaluated the degrees of parallelism that such a co-design can realistically exploit.
| Original language | English |
|---|---|
| Title of host publication | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
| Publisher | Springer Verlag |
| Pages | 464-467 |
| Number of pages | 4 |
| Volume | 1863 |
| ISBN (Print) | 9783540678588 |
| Publication status | Published - 2000 |
| Externally published | Yes |
| Event | 12th International Workshop on Languages and Compilers for Parallel Computing, LCPC 1999 - La Jolla, United States Duration: 1999 Aug 4 → 1999 Aug 6 |
Publication series
| Name | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
|---|---|
| Volume | 1863 |
| ISSN (Print) | 03029743 |
| ISSN (Electronic) | 16113349 |
Other
| Other | 12th International Workshop on Languages and Compilers for Parallel Computing, LCPC 1999 |
|---|---|
| Country | United States |
| City | La Jolla |
| Period | 99/8/4 → 99/8/6 |
Fingerprint
ASJC Scopus subject areas
- Computer Science(all)
- Theoretical Computer Science
Cite this
Compiling for speculative architectures. / Kim, Seon Wook; Eigenmann, Rudolf.
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 1863 Springer Verlag, 2000. p. 464-467 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 1863).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Compiling for speculative architectures
AU - Kim, Seon Wook
AU - Eigenmann, Rudolf
PY - 2000
Y1 - 2000
N2 - The traditional target machine of a parallelizing compiler can execute code sections either serially or in parallel. In contrast, tar- geting the generated code to a speculative parallel processor allows the compiler to recognize parallelism to the best of its abilities and leave other optimization decisions up to the processor's runtime detection me- chanisms. In this paper we show that simple improvements of the com- piler's speculative task selection method can already lead to signi_cant (up to 55%) improvement in speedup over that of a simple code genera- tor for a Multiscalar architecture. For an even more improved software/hardware cooperation we propose an interface that allows the compiler to inform the processor about fully parallel, serial, and speculative code sections as well as attributes of program variables. We have evaluated the degrees of parallelism that such a co-design can realistically exploit.
AB - The traditional target machine of a parallelizing compiler can execute code sections either serially or in parallel. In contrast, tar- geting the generated code to a speculative parallel processor allows the compiler to recognize parallelism to the best of its abilities and leave other optimization decisions up to the processor's runtime detection me- chanisms. In this paper we show that simple improvements of the com- piler's speculative task selection method can already lead to signi_cant (up to 55%) improvement in speedup over that of a simple code genera- tor for a Multiscalar architecture. For an even more improved software/hardware cooperation we propose an interface that allows the compiler to inform the processor about fully parallel, serial, and speculative code sections as well as attributes of program variables. We have evaluated the degrees of parallelism that such a co-design can realistically exploit.
UR - http://www.scopus.com/inward/record.url?scp=84948965894&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84948965894&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:84948965894
SN - 9783540678588
VL - 1863
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 464
EP - 467
BT - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
PB - Springer Verlag
ER -