Computation sharing programmable FIR filter for low-power and high-performance applications

Jongsun Park; Woopyo Jeong; Hamid Mahmoodi-Meimand; Yongtao Wang; Hunsoo Choo; Kaushik Roy

doi:10.1109/JSSC.2003.821785

Computation sharing programmable FIR filter for low-power and high-performance applications

Jongsun Park, Woopyo Jeong, Hamid Mahmoodi-Meimand, Yongtao Wang, Hunsoo Choo, Kaushik Roy

Research output: Contribution to journal › Article

72 Citations (Scopus)

Abstract

This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-μm technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm² area.

Original language	English
Pages (from-to)	348-357
Number of pages	10
Journal	IEEE Journal of Solid-State Circuits
Volume	39
Issue number	2
DOIs	https://doi.org/10.1109/JSSC.2003.821785
Publication status	Published - 2004 Feb
Externally published	Yes

Keywords

Computation sharing
Dual transition skewed logic
Programmable finite impulse response (FIR) filter

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/JSSC.2003.821785

Fingerprint Dive into the research topics of 'Computation sharing programmable FIR filter for low-power and high-performance applications'. Together they form a unique fingerprint.

Cite this

Park, J., Jeong, W., Mahmoodi-Meimand, H., Wang, Y., Choo, H., & Roy, K. (2004). Computation sharing programmable FIR filter for low-power and high-performance applications. IEEE Journal of Solid-State Circuits, 39(2), 348-357. https://doi.org/10.1109/JSSC.2003.821785

@article{c13123f98c2e40789a41c36f262bb98d,

title = "Computation sharing programmable FIR filter for low-power and high-performance applications",

abstract = "This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-μm technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm2 area.",

keywords = "Computation sharing, Dual transition skewed logic, Programmable finite impulse response (FIR) filter",

author = "Jongsun Park and Woopyo Jeong and Hamid Mahmoodi-Meimand and Yongtao Wang and Hunsoo Choo and Kaushik Roy",

year = "2004",

month = feb,

doi = "10.1109/JSSC.2003.821785",

language = "English",

volume = "39",

pages = "348--357",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "2",

}

TY - JOUR

T1 - Computation sharing programmable FIR filter for low-power and high-performance applications

AU - Park, Jongsun

AU - Jeong, Woopyo

AU - Mahmoodi-Meimand, Hamid

AU - Wang, Yongtao

AU - Choo, Hunsoo

AU - Roy, Kaushik

PY - 2004/2

Y1 - 2004/2

N2 - This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-μm technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm2 area.

AB - This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-μm technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm2 area.

KW - Computation sharing

KW - Dual transition skewed logic

KW - Programmable finite impulse response (FIR) filter

UR - http://www.scopus.com/inward/record.url?scp=1242330897&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=1242330897&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2003.821785

DO - 10.1109/JSSC.2003.821785

M3 - Article

AN - SCOPUS:1242330897

VL - 39

SP - 348

EP - 357

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 2

ER -