Abstract
This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-μm technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm2 area.
| Original language | English |
|---|---|
| Pages (from-to) | 348-357 |
| Number of pages | 10 |
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 39 |
| Issue number | 2 |
| DOIs | |
| Publication status | Published - 2004 Feb 1 |
| Externally published | Yes |
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Keywords
- Computation sharing
- Dual transition skewed logic
- Programmable finite impulse response (FIR) filter
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
Computation sharing programmable FIR filter for low-power and high-performance applications. / Park, Jongsun; Jeong, Woopyo; Mahmoodi-Meimand, Hamid; Wang, Yongtao; Choo, Hunsoo; Roy, Kaushik.
In: IEEE Journal of Solid-State Circuits, Vol. 39, No. 2, 01.02.2004, p. 348-357.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Computation sharing programmable FIR filter for low-power and high-performance applications
AU - Park, Jongsun
AU - Jeong, Woopyo
AU - Mahmoodi-Meimand, Hamid
AU - Wang, Yongtao
AU - Choo, Hunsoo
AU - Roy, Kaushik
PY - 2004/2/1
Y1 - 2004/2/1
N2 - This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-μm technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm2 area.
AB - This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-μm technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm2 area.
KW - Computation sharing
KW - Dual transition skewed logic
KW - Programmable finite impulse response (FIR) filter
UR - http://www.scopus.com/inward/record.url?scp=1242330897&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=1242330897&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2003.821785
DO - 10.1109/JSSC.2003.821785
M3 - Article
VL - 39
SP - 348
EP - 357
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 2
ER -