Computation sharing programmable FIR filter for low-power and high-performance applications

Jongsun Park; Woopyo Jeong; Hamid Mahmoodi-Meimand; Yongtao Wang; Hunsoo Choo; Kaushik Roy

doi:10.1109/JSSC.2003.821785

Computation sharing programmable FIR filter for low-power and high-performance applications

Jongsun Park, Woopyo Jeong, Hamid Mahmoodi-Meimand, Yongtao Wang, Hunsoo Choo, Kaushik Roy

Research output: Contribution to journal › Article › peer-review

76 Citations (Scopus)

Abstract

This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-μm technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm² area.

Original language	English
Pages (from-to)	348-357
Number of pages	10
Journal	IEEE Journal of Solid-State Circuits
Volume	39
Issue number	2
DOIs	https://doi.org/10.1109/JSSC.2003.821785
Publication status	Published - 2004 Feb
Externally published	Yes

Keywords

Computation sharing
Dual transition skewed logic
Programmable finite impulse response (FIR) filter

ASJC Scopus subject areas

Electrical and Electronic Engineering

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AU - Choo, Hunsoo

AU - Roy, Kaushik

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AB - This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-μm technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm2 area.

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Computation sharing programmable FIR filter for low-power and high-performance applications

Abstract

Keywords

ASJC Scopus subject areas

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