Content addressable memory based binarized neural network accelerator using time-domain signal processing

Woong Choi, Kwanghyo Jeong, Kyungrak Choi, Kyeongho Lee, Jongsun Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Binarized neural network (BNN) is one of the most promising solution for low-cost convolutional neural network acceleration. Since BNN is based on binarized bit-level operations, there exist great opportunities to reduce power-hungry data transfers and complex arithmetic operations. In this paper, we propose a content addressable memory (CAM) based BNN accelerator. By using time-domain signal processing, the huge convolution operations of BNN can be effectively replaced to the CAM search operation. In addition, thanks to fully parallel search of CAM, the parallel convolution operations for non-overlapped filtering window is enabled for high throughput data processing. To verify the effectiveness of the proposed CAM based BNN accelerator, the convolutional layer of LeNet-5 model has been implemented using 65nm CMOS technology. The implementation results show that the proposed BNN accelerator achieves 9.4% and 38.5% of area and energy savings, respectively. The parallel convolution operation of the proposed approach also shows 2.4x improved processing time.

Original languageEnglish
Title of host publicationProceedings of the 55th Annual Design Automation Conference, DAC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
VolumePart F137710
ISBN (Print)9781450357005
DOIs
Publication statusPublished - 2018 Jun 24
Event55th Annual Design Automation Conference, DAC 2018 - San Francisco, United States
Duration: 2018 Jun 242018 Jun 29

Other

Other55th Annual Design Automation Conference, DAC 2018
CountryUnited States
CitySan Francisco
Period18/6/2418/6/29

Keywords

  • Binarized neural network
  • Content addressable memory
  • Timedomain signal processing

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modelling and Simulation

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  • Cite this

    Choi, W., Jeong, K., Choi, K., Lee, K., & Park, J. (2018). Content addressable memory based binarized neural network accelerator using time-domain signal processing. In Proceedings of the 55th Annual Design Automation Conference, DAC 2018 (Vol. Part F137710). [a138] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/3195970.3196014