Covered source-channel tunnel field-effect transistors with trench gate structures

Sola Woo, Sangsig Kim

Research output: Contribution to journalArticle

Abstract

We propose a new design for covered source-channel tunnel field-effect transistors (CSC-TFETs) with trench gate structures. The I-V characteristics, on/off current ratio, subthreshold swing, and band-to-band tunneling rate are analyzed using a commercial device simulator. Our proposed CSC-TFETs exhibit an on/off current ratio of approximately 1010, an on-current of approximately 10-5 A/μm at room temperature, and a subthreshold swing of less than 40 mV/decade. In addition, the on-current of the CSC-TFETs is ∼233 times that of conventional TFETs, demonstrating that the switching characteristics are superior to those of other silicon-based TFETs. Moreover, a CSC-TFET inverter is characterized by SPICE calibration and provides a high frequency of approximately 1 GHz at a supply voltage of 1.0 V.

Original languageEnglish
Article number8554273
Pages (from-to)114-118
Number of pages5
JournalIEEE Transactions on Nanotechnology
Volume18
DOIs
Publication statusPublished - 2019 Jan 1

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Field effect transistors
Tunnels
SPICE
Simulators
Calibration
Silicon
Electric potential
Temperature

Keywords

  • covered source-channel TFET
  • SPICE model
  • TCAD simulation
  • trench gate
  • Tunnel field-effect transistors

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

Covered source-channel tunnel field-effect transistors with trench gate structures. / Woo, Sola; Kim, Sangsig.

In: IEEE Transactions on Nanotechnology, Vol. 18, 8554273, 01.01.2019, p. 114-118.

Research output: Contribution to journalArticle

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