Current adjustable clock distribution network scheme for GDDR5

S. B. Lim, S. Hwang, J. You, Y. Baek, Chulwoo Kim

Research output: Contribution to journalArticle

Abstract

Presented is a current adjustable clock distribution network for GDDR5. In general, GDDR5 uses a current mode logic (CML) buffer as the global driver of the clock distribution. The widefrequency range conventional CML buffer is designed to the fastest frequency. However, the CML buffer consumes constant current at all frequencies. For this reason, the conventional buffer dissipates current more than necessary at low frequencies. A proposed current adjustable clock distribution network scheme adjusts the amount of the current consumption of the global driver according to the clock frequency. The proposed scheme is implemented in 65 nm CMOS technology, reduces power consumption by 17.7% in the wide frequency range from an average 10.26 mW of the conventional scheme to 8.44 mW.

Original languageEnglish
Pages (from-to)689-691
Number of pages3
JournalElectronics Letters
Volume49
Issue number11
DOIs
Publication statusPublished - 2013 May 23

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Clock distribution networks
Clocks
Electric power utilization

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Current adjustable clock distribution network scheme for GDDR5. / Lim, S. B.; Hwang, S.; You, J.; Baek, Y.; Kim, Chulwoo.

In: Electronics Letters, Vol. 49, No. 11, 23.05.2013, p. 689-691.

Research output: Contribution to journalArticle

Lim, S. B. ; Hwang, S. ; You, J. ; Baek, Y. ; Kim, Chulwoo. / Current adjustable clock distribution network scheme for GDDR5. In: Electronics Letters. 2013 ; Vol. 49, No. 11. pp. 689-691.
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