Customized SRAM design for low power video code applications

Sangkyu Lee, Hoyoung Tang, Kyungrak Choi, Jongsun Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, an embedded SRAM architecture of Video application is proposed to reduce the power consumption. By analyzing the general read and write access patterns, the embedded memory is customized to reduce power consumption while achieving general FIFO operations. Some of the signal activations and the Pseudo-read operations are removed in FIFO. According to the simulation results with 65nm CMOS process, the proposed embedded memory for line buffer achieves 17.62% power savings with 3.72% overhead compared to the conventional embedded SRAM approaches.

Original languageEnglish
Title of host publicationISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages79-80
Number of pages2
ISBN (Electronic)9781467393089
DOIs
Publication statusPublished - 2016 Dec 27
Event13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of
Duration: 2016 Oct 232016 Oct 26

Other

Other13th International SoC Design Conference, ISOCC 2016
CountryKorea, Republic of
CityJeju
Period16/10/2316/10/26

Keywords

  • Embedded memory
  • Line buffer
  • Low power operation
  • Multimedia
  • SRAM

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Instrumentation

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  • Cite this

    Lee, S., Tang, H., Choi, K., & Park, J. (2016). Customized SRAM design for low power video code applications. In ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things (pp. 79-80). [7799742] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2016.7799742