Data dependent precharging dynamic chain architecture for low power and high speed adders

Woo Hyun Paik, In Chul Hwang, Jae Wan Kim, Soo-Won Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a power efficient dynamic chain adder based on a Data Dependent Precharging (DDP) algorithm. It suppresses spurious transitions due to the unconditional precharging of outputs during the `precharge' mode. A 64-bit adder has been designed using the DDP dynamic chain architecture. Simulation results confirm that it operates at 270 MHz with 0.105 mW/MHz power consumption at 3.3 V supply. It reduces power by 36% without speed degradation.

Original languageEnglish
Title of host publicationProceedings of the Annual IEEE International ASIC Conference and Exhibit
EditorsP.R. Mukund, R. Sridhar, T. Gabara, J.D. Carothers
PublisherIEEE
Pages173-177
Number of pages5
Publication statusPublished - 1997
Externally publishedYes
EventProceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit - Portland, OR, USA
Duration: 1997 Sep 71997 Sep 10

Other

OtherProceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit
CityPortland, OR, USA
Period97/9/797/9/10

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Paik, W. H., Hwang, I. C., Kim, J. W., & Kim, S-W. (1997). Data dependent precharging dynamic chain architecture for low power and high speed adders. In P. R. Mukund, R. Sridhar, T. Gabara, & J. D. Carothers (Eds.), Proceedings of the Annual IEEE International ASIC Conference and Exhibit (pp. 173-177). IEEE.