Data dependent precharging dynamic chain architecture for low power and high speed adders

Woo Hyun Paik; In Chul Hwang; Jae Wan Kim; Soo Won Kim

Data dependent precharging dynamic chain architecture for low power and high speed adders

Woo Hyun Paik, In Chul Hwang, Jae Wan Kim, Soo Won Kim

Research output: Contribution to journal › Conference article › peer-review

Abstract

This paper presents a power efficient dynamic chain adder based on a Data Dependent Precharging (DDP) algorithm. It suppresses spurious transitions due to the unconditional precharging of outputs during the `precharge' mode. A 64-bit adder has been designed using the DDP dynamic chain architecture. Simulation results confirm that it operates at 270 MHz with 0.105 mW/MHz power consumption at 3.3 V supply. It reduces power by 36% without speed degradation.

Original language	English
Pages (from-to)	173-177
Number of pages	5
Journal	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
Publication status	Published - 1997
Externally published	Yes
Event	Proceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit - Portland, OR, USA Duration: 1997 Sept 7 → 1997 Sept 10

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "Data dependent precharging dynamic chain architecture for low power and high speed adders",

abstract = "This paper presents a power efficient dynamic chain adder based on a Data Dependent Precharging (DDP) algorithm. It suppresses spurious transitions due to the unconditional precharging of outputs during the `precharge' mode. A 64-bit adder has been designed using the DDP dynamic chain architecture. Simulation results confirm that it operates at 270 MHz with 0.105 mW/MHz power consumption at 3.3 V supply. It reduces power by 36% without speed degradation.",

author = "Paik, {Woo Hyun} and Hwang, {In Chul} and Kim, {Jae Wan} and Kim, {Soo Won}",

year = "1997",

language = "English",

pages = "173--177",

journal = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",

issn = "1063-0988",

note = "Proceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit ; Conference date: 07-09-1997 Through 10-09-1997",

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AU - Paik, Woo Hyun

AU - Hwang, In Chul

AU - Kim, Jae Wan

AU - Kim, Soo Won

PY - 1997

Y1 - 1997

N2 - This paper presents a power efficient dynamic chain adder based on a Data Dependent Precharging (DDP) algorithm. It suppresses spurious transitions due to the unconditional precharging of outputs during the `precharge' mode. A 64-bit adder has been designed using the DDP dynamic chain architecture. Simulation results confirm that it operates at 270 MHz with 0.105 mW/MHz power consumption at 3.3 V supply. It reduces power by 36% without speed degradation.

AB - This paper presents a power efficient dynamic chain adder based on a Data Dependent Precharging (DDP) algorithm. It suppresses spurious transitions due to the unconditional precharging of outputs during the `precharge' mode. A 64-bit adder has been designed using the DDP dynamic chain architecture. Simulation results confirm that it operates at 270 MHz with 0.105 mW/MHz power consumption at 3.3 V supply. It reduces power by 36% without speed degradation.

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M3 - Conference article

AN - SCOPUS:0030649392

SN - 1063-0988

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JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

T2 - Proceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit

Y2 - 7 September 1997 through 10 September 1997

ER -

Data dependent precharging dynamic chain architecture for low power and high speed adders

Abstract

ASJC Scopus subject areas

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