Data dependent precharging dynamic chain architecture for low power and high speed adders

Woo Hyun Paik, In Chul Hwang, Jae Wan Kim, Soo Won Kim

Research output: Contribution to journalConference article

Abstract

This paper presents a power efficient dynamic chain adder based on a Data Dependent Precharging (DDP) algorithm. It suppresses spurious transitions due to the unconditional precharging of outputs during the `precharge' mode. A 64-bit adder has been designed using the DDP dynamic chain architecture. Simulation results confirm that it operates at 270 MHz with 0.105 mW/MHz power consumption at 3.3 V supply. It reduces power by 36% without speed degradation.

Original languageEnglish
Pages (from-to)173-177
Number of pages5
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
Publication statusPublished - 1997
EventProceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit - Portland, OR, USA
Duration: 1997 Sep 71997 Sep 10

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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