This paper presents a power efficient dynamic chain adder based on a Data Dependent Precharging (DDP) algorithm. It suppresses spurious transitions due to the unconditional precharging of outputs during the `precharge' mode. A 64-bit adder has been designed using the DDP dynamic chain architecture. Simulation results confirm that it operates at 270 MHz with 0.105 mW/MHz power consumption at 3.3 V supply. It reduces power by 36% without speed degradation.
|Number of pages||5|
|Journal||Proceedings of the Annual IEEE International ASIC Conference and Exhibit|
|Publication status||Published - 1997|
|Event||Proceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit - Portland, OR, USA|
Duration: 1997 Sep 7 → 1997 Sep 10
ASJC Scopus subject areas
- Electrical and Electronic Engineering