DCT processor architecture based on computation sharing

Soonkeon Kwon; Jongsun Park; K. Roy

doi:10.1109/OCCSC.2002.1029070

DCT processor architecture based on computation sharing

Soonkeon Kwon, Jongsun Park, K. Roy

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

In this paper, we present a new discrete cosine transform (DCT) processor architecture using computation sharing multiplication (CSHM). We introduce a computation sharing multiplier based DCT architecture to achieve image quality and hardware complexity trade-off and analyze the performance. Comparison of the performance, area and power consumption with a DA (distributed arithmetic) based DCT architecture is performed. The result shows that the proposed architecture improves power consumption by 14% and area by 41% with acceptable image quality degradation.

Original language	English
Title of host publication	ICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings
Editors	A. S. Korotkov
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	162-165
Number of pages	4
ISBN (Electronic)	5742202601, 9785742202608
DOIs	https://doi.org/10.1109/OCCSC.2002.1029070
Publication status	Published - 2002
Externally published	Yes
Event	1st IEEE International Conference on Circuits and Systems for Communications, ICCSC 2002 - St.Petersburg, Russian Federation Duration: 2002 Jun 26 → 2002 Jun 28

Publication series

Name	ICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings
Volume	2002-June

Other

Other	1st IEEE International Conference on Circuits and Systems for Communications, ICCSC 2002
Country/Territory	Russian Federation
City	St.Petersburg
Period	02/6/26 → 02/6/28

ASJC Scopus subject areas

Computer Networks and Communications
Electrical and Electronic Engineering

Access to Document

10.1109/OCCSC.2002.1029070

Cite this

Kwon, S., Park, J., & Roy, K. (2002). DCT processor architecture based on computation sharing. In A. S. Korotkov (Ed.), ICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings (pp. 162-165). [1029070] (ICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings; Vol. 2002-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/OCCSC.2002.1029070

DCT processor architecture based on computation sharing. / Kwon, Soonkeon; Park, Jongsun; Roy, K.

ICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings. ed. / A. S. Korotkov. Institute of Electrical and Electronics Engineers Inc., 2002. p. 162-165 1029070 (ICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings; Vol. 2002-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kwon, S, Park, J & Roy, K 2002, DCT processor architecture based on computation sharing. in AS Korotkov (ed.), ICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings., 1029070, ICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings, vol. 2002-June, Institute of Electrical and Electronics Engineers Inc., pp. 162-165, 1st IEEE International Conference on Circuits and Systems for Communications, ICCSC 2002, St.Petersburg, Russian Federation, 02/6/26. https://doi.org/10.1109/OCCSC.2002.1029070

Kwon S, Park J, Roy K. DCT processor architecture based on computation sharing. In Korotkov AS, editor, ICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2002. p. 162-165. 1029070. (ICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings). https://doi.org/10.1109/OCCSC.2002.1029070

Kwon, Soonkeon ; Park, Jongsun ; Roy, K. / DCT processor architecture based on computation sharing. ICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings. editor / A. S. Korotkov. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 162-165 (ICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings).

@inproceedings{d9dbd446710041489e5fff3616af5b95,

title = "DCT processor architecture based on computation sharing",

abstract = "In this paper, we present a new discrete cosine transform (DCT) processor architecture using computation sharing multiplication (CSHM). We introduce a computation sharing multiplier based DCT architecture to achieve image quality and hardware complexity trade-off and analyze the performance. Comparison of the performance, area and power consumption with a DA (distributed arithmetic) based DCT architecture is performed. The result shows that the proposed architecture improves power consumption by 14% and area by 41% with acceptable image quality degradation.",

author = "Soonkeon Kwon and Jongsun Park and K. Roy",

note = "Funding Information: This research is funded in parts by DARPA. Publisher Copyright: {\textcopyright} 2002 St. Petersburg State Poly Univ. Copyright: Copyright 2017 Elsevier B.V., All rights reserved.; 1st IEEE International Conference on Circuits and Systems for Communications, ICCSC 2002 ; Conference date: 26-06-2002 Through 28-06-2002",

year = "2002",

doi = "10.1109/OCCSC.2002.1029070",

language = "English",

series = "ICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "162--165",

editor = "Korotkov, {A. S.}",

booktitle = "ICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings",

}

TY - GEN

T1 - DCT processor architecture based on computation sharing

AU - Kwon, Soonkeon

AU - Park, Jongsun

AU - Roy, K.

PY - 2002

Y1 - 2002

N2 - In this paper, we present a new discrete cosine transform (DCT) processor architecture using computation sharing multiplication (CSHM). We introduce a computation sharing multiplier based DCT architecture to achieve image quality and hardware complexity trade-off and analyze the performance. Comparison of the performance, area and power consumption with a DA (distributed arithmetic) based DCT architecture is performed. The result shows that the proposed architecture improves power consumption by 14% and area by 41% with acceptable image quality degradation.

AB - In this paper, we present a new discrete cosine transform (DCT) processor architecture using computation sharing multiplication (CSHM). We introduce a computation sharing multiplier based DCT architecture to achieve image quality and hardware complexity trade-off and analyze the performance. Comparison of the performance, area and power consumption with a DA (distributed arithmetic) based DCT architecture is performed. The result shows that the proposed architecture improves power consumption by 14% and area by 41% with acceptable image quality degradation.

UR - http://www.scopus.com/inward/record.url?scp=84990946926&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84990946926&partnerID=8YFLogxK

U2 - 10.1109/OCCSC.2002.1029070

DO - 10.1109/OCCSC.2002.1029070

M3 - Conference contribution

AN - SCOPUS:84990946926

T3 - ICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings

SP - 162

EP - 165

BT - ICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings

A2 - Korotkov, A. S.

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 1st IEEE International Conference on Circuits and Systems for Communications, ICCSC 2002

Y2 - 26 June 2002 through 28 June 2002

ER -

DCT processor architecture based on computation sharing

Abstract

Publication series

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this