DCT processor architecture based on computation sharing

Soonkeon Kwon, Jongsun Park, K. Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

In this paper, we present a new discrete cosine transform (DCT) processor architecture using computation sharing multiplication (CSHM). We introduce a computation sharing multiplier based DCT architecture to achieve image quality and hardware complexity trade-off and analyze the performance. Comparison of the performance, area and power consumption with a DA (distributed arithmetic) based DCT architecture is performed. The result shows that the proposed architecture improves power consumption by 14% and area by 41% with acceptable image quality degradation.

Original languageEnglish
Title of host publicationICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages162-165
Number of pages4
Volume2002-June
ISBN (Electronic)5742202601, 9785742202608
DOIs
Publication statusPublished - 2002
Externally publishedYes
Event1st IEEE International Conference on Circuits and Systems for Communications, ICCSC 2002 - St.Petersburg, Russian Federation
Duration: 2002 Jun 262002 Jun 28

Other

Other1st IEEE International Conference on Circuits and Systems for Communications, ICCSC 2002
CountryRussian Federation
CitySt.Petersburg
Period02/6/2602/6/28

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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    Kwon, S., Park, J., & Roy, K. (2002). DCT processor architecture based on computation sharing. In ICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings (Vol. 2002-June, pp. 162-165). [1029070] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/OCCSC.2002.1029070