Abstract
In this paper, we present a new discrete cosine transform (DCT) processor architecture using computation sharing multiplication (CSHM). We introduce a computation sharing multiplier based DCT architecture to achieve image quality and hardware complexity trade-off and analyze the performance. Comparison of the performance, area and power consumption with a DA (distributed arithmetic) based DCT architecture is performed. The result shows that the proposed architecture improves power consumption by 14% and area by 41% with acceptable image quality degradation.
| Original language | English |
|---|---|
| Title of host publication | ICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 162-165 |
| Number of pages | 4 |
| Volume | 2002-June |
| ISBN (Electronic) | 5742202601, 9785742202608 |
| DOIs | |
| Publication status | Published - 2002 |
| Externally published | Yes |
| Event | 1st IEEE International Conference on Circuits and Systems for Communications, ICCSC 2002 - St.Petersburg, Russian Federation Duration: 2002 Jun 26 → 2002 Jun 28 |
Other
| Other | 1st IEEE International Conference on Circuits and Systems for Communications, ICCSC 2002 |
|---|---|
| Country | Russian Federation |
| City | St.Petersburg |
| Period | 02/6/26 → 02/6/28 |
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ASJC Scopus subject areas
- Computer Networks and Communications
- Electrical and Electronic Engineering
Cite this
DCT processor architecture based on computation sharing. / Kwon, Soonkeon; Park, Jongsun; Roy, K.
ICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings. Vol. 2002-June Institute of Electrical and Electronics Engineers Inc., 2002. p. 162-165 1029070.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
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TY - GEN
T1 - DCT processor architecture based on computation sharing
AU - Kwon, Soonkeon
AU - Park, Jongsun
AU - Roy, K.
PY - 2002
Y1 - 2002
N2 - In this paper, we present a new discrete cosine transform (DCT) processor architecture using computation sharing multiplication (CSHM). We introduce a computation sharing multiplier based DCT architecture to achieve image quality and hardware complexity trade-off and analyze the performance. Comparison of the performance, area and power consumption with a DA (distributed arithmetic) based DCT architecture is performed. The result shows that the proposed architecture improves power consumption by 14% and area by 41% with acceptable image quality degradation.
AB - In this paper, we present a new discrete cosine transform (DCT) processor architecture using computation sharing multiplication (CSHM). We introduce a computation sharing multiplier based DCT architecture to achieve image quality and hardware complexity trade-off and analyze the performance. Comparison of the performance, area and power consumption with a DA (distributed arithmetic) based DCT architecture is performed. The result shows that the proposed architecture improves power consumption by 14% and area by 41% with acceptable image quality degradation.
UR - http://www.scopus.com/inward/record.url?scp=84990946926&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84990946926&partnerID=8YFLogxK
U2 - 10.1109/OCCSC.2002.1029070
DO - 10.1109/OCCSC.2002.1029070
M3 - Conference contribution
AN - SCOPUS:84990946926
VL - 2002-June
SP - 162
EP - 165
BT - ICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
ER -