Design and implementation of dual processor block with shared external cache memory

Soo-Won Kim, Hanseok Ko, Woo Jong Hahn, Jong S. Hahm

Research output: Contribution to journalArticle

Abstract

The availability of low cost, high performance microprocessors has led to various designs of shared memory multiprocessor systems. As a result, commercial products which are based on shared memory have been proliferated. Such a multiprocessor system is heavily influenced by the structure of memory system and it is not difficult to find that most configurations include local cache memories. The more processors a system carries, the larger local cache memory is needed to maintain the traffic to and from the shared memory at reasonable level. The implementation of local cache memories, however, is not a simple task because of environmental limitations. In particular, the general lack of board space availability presents a formidable problem. A cache memory system usually needs space mostly to support its complex control logic circuits for the cache itself and network interfaces like snooping logic circuits for shared bus. Although packaging can be made denser to reduce system size, there are still multiple processors per board. It requires a more area-efficient cache memory architecture. This paper presents a design of shared cache for dual processor board of bus-based symmetric multiprocessors. The design and implementation issues are described first and then the evaluation and measurement results are discussed. The shared cache proposed in this paper has been determined to be quite area-efficient without the significant loss of throughput and scalability. It has been implemented as a plug-in unit for TICOM, a prevalent commercial multiprocessor system.

Original languageEnglish
Pages (from-to)595-605
Number of pages11
JournalMicroprocessors and Microsystems
Volume20
Issue number10
Publication statusPublished - 1997 Jul 1

Fingerprint

Cache memory
Data storage equipment
Logic circuits
Availability
Memory architecture
Interfaces (computer)
Microprocessor chips
Scalability
Packaging
Computer systems
Throughput
Costs

Keywords

  • Bus utilization
  • Multiprocessor
  • On-chip cache
  • Pipelined bus protocol
  • Shared bus
  • Shared cache
  • TICOM

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Software
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Design and implementation of dual processor block with shared external cache memory. / Kim, Soo-Won; Ko, Hanseok; Hahn, Woo Jong; Hahm, Jong S.

In: Microprocessors and Microsystems, Vol. 20, No. 10, 01.07.1997, p. 595-605.

Research output: Contribution to journalArticle

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