Design and implementation of unified hardware for 128-bit block ciphers ARIA and AES

Bonseok Koo, Gwonho Ryu, Taejoo Chang, Sangjin Lee

Research output: Contribution to journalArticle

8 Citations (Scopus)


ARIA and the Advanced Encryption Standard (AES) are next generation standard block cipher algorithms of Korea and the US, respectively. This letter presents an areaefficient unified hardware architecture of ARIA and AES. Both algorithms have 128-bit substitution permutation network (SPN) structures, and their substitution and permutation layers could be efficiently merged. Therefore, we propose a 128-bit processor architecture with resource sharing, which is capable of processing ARIA and AES. This is the first architecture which supports both algorithms. Furthermore, it requires only 19,056 logic gates and encrypts data at 720 Mbps and 1,047 Mbps for ARIA and AES, respectively.

Original languageEnglish
Pages (from-to)820-822
Number of pages3
JournalETRI Journal
Issue number6
Publication statusPublished - 2007 Dec 1



  • AES
  • ARIA
  • Hardware architecture
  • Resource sharing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Networks and Communications

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