Design issues and optimization in DisplayPort link layer implementation

Jaegeun Oh, Seon Wook Kim, Taejin Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Nowadays, the advanced digital display technology makes display devices support extreme high quality video like full HD. In order to support the quality, a communication interface of the display devices must provide a high bandwidth in video transmission. The DisplayPort, as one of the solutions, was proposed as an industry standard to transmit high color depths, refresh rates and display resolution. In this paper, we present several optimization methods from our experience to prototype a datalink layer of the DisplayPort interface based on the DisplayPort standard version 1.1a of VESA. Also, we show that our system consumes 205.3K logic cells and 55.6mW power with Samsung 0.13um library.

Original languageEnglish
Title of host publicationProceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Pages188-191
Number of pages4
DOIs
Publication statusPublished - 2010
Event2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur, Malaysia
Duration: 2010 Dec 62010 Dec 9

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

Other2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
CountryMalaysia
CityKuala Lumpur
Period10/12/610/12/9

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Oh, J., Kim, S. W., & Kim, T. (2010). Design issues and optimization in DisplayPort link layer implementation. In Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 (pp. 188-191). [5774908] (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2010.5774908