Design issues and optimization in DisplayPort link layer implementation

Jaegeun Oh; Seon Wook Kim; Taejin Kim

doi:10.1109/APCCAS.2010.5774908

Design issues and optimization in DisplayPort link layer implementation

Jaegeun Oh, Seon Wook Kim, Taejin Kim

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Nowadays, the advanced digital display technology makes display devices support extreme high quality video like full HD. In order to support the quality, a communication interface of the display devices must provide a high bandwidth in video transmission. The DisplayPort, as one of the solutions, was proposed as an industry standard to transmit high color depths, refresh rates and display resolution. In this paper, we present several optimization methods from our experience to prototype a datalink layer of the DisplayPort interface based on the DisplayPort standard version 1.1a of VESA. Also, we show that our system consumes 205.3K logic cells and 55.6mW power with Samsung 0.13um library.

Original language	English
Title of host publication	Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Pages	188-191
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2010.5774908
Publication status	Published - 2010
Event	2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur, Malaysia Duration: 2010 Dec 6 → 2010 Dec 9

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

Other	2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Country/Territory	Malaysia
City	Kuala Lumpur
Period	10/12/6 → 10/12/9

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/APCCAS.2010.5774908

Cite this

Design issues and optimization in DisplayPort link layer implementation. / Oh, Jaegeun; Kim, Seon Wook; Kim, Taejin.

Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010. 2010. p. 188-191 5774908 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Oh, J, Kim, SW & Kim, T 2010, Design issues and optimization in DisplayPort link layer implementation. in Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010., 5774908, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 188-191, 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010, Kuala Lumpur, Malaysia, 10/12/6. https://doi.org/10.1109/APCCAS.2010.5774908

@inproceedings{ead447bc4e5b444abe88f7de594be58c,

title = "Design issues and optimization in DisplayPort link layer implementation",

abstract = "Nowadays, the advanced digital display technology makes display devices support extreme high quality video like full HD. In order to support the quality, a communication interface of the display devices must provide a high bandwidth in video transmission. The DisplayPort, as one of the solutions, was proposed as an industry standard to transmit high color depths, refresh rates and display resolution. In this paper, we present several optimization methods from our experience to prototype a datalink layer of the DisplayPort interface based on the DisplayPort standard version 1.1a of VESA. Also, we show that our system consumes 205.3K logic cells and 55.6mW power with Samsung 0.13um library.",

author = "Jaegeun Oh and Kim, {Seon Wook} and Taejin Kim",

year = "2010",

doi = "10.1109/APCCAS.2010.5774908",

language = "English",

isbn = "9781424474561",

series = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",

pages = "188--191",

booktitle = "Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010",

note = "2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 ; Conference date: 06-12-2010 Through 09-12-2010",

}

TY - GEN

T1 - Design issues and optimization in DisplayPort link layer implementation

AU - Oh, Jaegeun

AU - Kim, Seon Wook

AU - Kim, Taejin

PY - 2010

Y1 - 2010

N2 - Nowadays, the advanced digital display technology makes display devices support extreme high quality video like full HD. In order to support the quality, a communication interface of the display devices must provide a high bandwidth in video transmission. The DisplayPort, as one of the solutions, was proposed as an industry standard to transmit high color depths, refresh rates and display resolution. In this paper, we present several optimization methods from our experience to prototype a datalink layer of the DisplayPort interface based on the DisplayPort standard version 1.1a of VESA. Also, we show that our system consumes 205.3K logic cells and 55.6mW power with Samsung 0.13um library.

AB - Nowadays, the advanced digital display technology makes display devices support extreme high quality video like full HD. In order to support the quality, a communication interface of the display devices must provide a high bandwidth in video transmission. The DisplayPort, as one of the solutions, was proposed as an industry standard to transmit high color depths, refresh rates and display resolution. In this paper, we present several optimization methods from our experience to prototype a datalink layer of the DisplayPort interface based on the DisplayPort standard version 1.1a of VESA. Also, we show that our system consumes 205.3K logic cells and 55.6mW power with Samsung 0.13um library.

UR - http://www.scopus.com/inward/record.url?scp=79959278554&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79959278554&partnerID=8YFLogxK

U2 - 10.1109/APCCAS.2010.5774908

DO - 10.1109/APCCAS.2010.5774908

M3 - Conference contribution

AN - SCOPUS:79959278554

SN - 9781424474561

T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

SP - 188

EP - 191

BT - Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010

T2 - 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010

Y2 - 6 December 2010 through 9 December 2010

ER -

Design issues and optimization in DisplayPort link layer implementation

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