Design of a 169% locking-range frequency divider with programmable input sensitivity

Byeonghak Jo; Hyeonseok Hwang; Junil Moon; Seung Baek Park; Soo-Won Kim

doi:10.1109/ICCE.2015.7066389

Design of a 169% locking-range frequency divider with programmable input sensitivity

Byeonghak Jo, Hyeonseok Hwang, Junil Moon, Seung Baek Park, Soo-Won Kim

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A wide locking-range frequency divider with programmable input sensitivity is presented in this paper. The frequency divider consists of two D flip-flop-based current mode logic latches and a current control circuit. The current control circuit adjusts the current ratio of the sampling pair and the latching pair, while the total current is maintained as a constant. The current control circuit enables the self-oscillation frequency to be adapted to the input frequency. As a result, the divider has wide locking range below -10 dBm input level. The proposed frequency divider is implemented in 0.18 um standard CMOS technology, and the measurement results show a 169% frequency locking range of between 0.5 and 6 GHz at an input power of - 10 dBm while consuming 7.2 mW from a 1.8 V supply voltage.

Original language	English
Title of host publication	2015 IEEE International Conference on Consumer Electronics, ICCE 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	222-223
Number of pages	2
ISBN (Print)	9781479975426
DOIs	https://doi.org/10.1109/ICCE.2015.7066389
Publication status	Published - 2015 Mar 23
Event	2015 IEEE International Conference on Consumer Electronics, ICCE 2015 - Las Vegas, United States Duration: 2015 Jan 9 → 2015 Jan 12

Other

Other	2015 IEEE International Conference on Consumer Electronics, ICCE 2015
Country	United States
City	Las Vegas
Period	15/1/9 → 15/1/12

Keywords

current mode logic latch
divide-by-2
frequency divider
wide locking range

ASJC Scopus subject areas

Computer Networks and Communications
Electrical and Electronic Engineering
Industrial and Manufacturing Engineering

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Design of a 169% locking-range frequency divider with programmable input sensitivity. / Jo, Byeonghak; Hwang, Hyeonseok; Moon, Junil; Park, Seung Baek; Kim, Soo-Won.

2015 IEEE International Conference on Consumer Electronics, ICCE 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 222-223 7066389.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Jo, B, Hwang, H, Moon, J, Park, SB & Kim, S-W 2015, Design of a 169% locking-range frequency divider with programmable input sensitivity. in 2015 IEEE International Conference on Consumer Electronics, ICCE 2015., 7066389, Institute of Electrical and Electronics Engineers Inc., pp. 222-223, 2015 IEEE International Conference on Consumer Electronics, ICCE 2015, Las Vegas, United States, 15/1/9. https://doi.org/10.1109/ICCE.2015.7066389

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abstract = "A wide locking-range frequency divider with programmable input sensitivity is presented in this paper. The frequency divider consists of two D flip-flop-based current mode logic latches and a current control circuit. The current control circuit adjusts the current ratio of the sampling pair and the latching pair, while the total current is maintained as a constant. The current control circuit enables the self-oscillation frequency to be adapted to the input frequency. As a result, the divider has wide locking range below -10 dBm input level. The proposed frequency divider is implemented in 0.18 um standard CMOS technology, and the measurement results show a 169% frequency locking range of between 0.5 and 6 GHz at an input power of - 10 dBm while consuming 7.2 mW from a 1.8 V supply voltage.",

keywords = "current mode logic latch, divide-by-2, frequency divider, wide locking range",

author = "Byeonghak Jo and Hyeonseok Hwang and Junil Moon and Park, {Seung Baek} and Soo-Won Kim",

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N2 - A wide locking-range frequency divider with programmable input sensitivity is presented in this paper. The frequency divider consists of two D flip-flop-based current mode logic latches and a current control circuit. The current control circuit adjusts the current ratio of the sampling pair and the latching pair, while the total current is maintained as a constant. The current control circuit enables the self-oscillation frequency to be adapted to the input frequency. As a result, the divider has wide locking range below -10 dBm input level. The proposed frequency divider is implemented in 0.18 um standard CMOS technology, and the measurement results show a 169% frequency locking range of between 0.5 and 6 GHz at an input power of - 10 dBm while consuming 7.2 mW from a 1.8 V supply voltage.

AB - A wide locking-range frequency divider with programmable input sensitivity is presented in this paper. The frequency divider consists of two D flip-flop-based current mode logic latches and a current control circuit. The current control circuit adjusts the current ratio of the sampling pair and the latching pair, while the total current is maintained as a constant. The current control circuit enables the self-oscillation frequency to be adapted to the input frequency. As a result, the divider has wide locking range below -10 dBm input level. The proposed frequency divider is implemented in 0.18 um standard CMOS technology, and the measurement results show a 169% frequency locking range of between 0.5 and 6 GHz at an input power of - 10 dBm while consuming 7.2 mW from a 1.8 V supply voltage.

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Design of a 169% locking-range frequency divider with programmable input sensitivity

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Keywords

ASJC Scopus subject areas

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