Design of a bus-based shared-memory multiprocessor DICE

Gyungho Lee, Bland W. Quattlebaum, Sangyeun Cho, Larry L. Kinney

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

DICE is a shared-bus multiprocessor based on a distributed shared-memory architecture, known as cache-only memory architecture (COMA). Unlike previous COMA proposals for large-scale multiprocessing, DICE utilizes COMA to effectively decrease the speed gap between modem high-performance microprocessors and the bus. DICE tries to optimize COMA for a shared-bus medium, in particular to reduce detrimental effects of the cache coherence and the 'last memory block' problem on replacement. In this paper, we present a global bus design of DICE based on the IEEE futurebus + backplane bus and the Texas Instruments chip-set. Our design demonstrates that necessary bus transactions for DICE can be done efficiently with existing standard bus signals. Considering the benefits of COMA and the moderate design complexity it adds to the conventional shared-bus multiprocessor design, a bus-based COMA multiprocessor, such as DICE, can become a viable candidate for future shared-bus multiprocessor designs.

Original languageEnglish
Pages (from-to)403-411
Number of pages9
JournalMicroprocessors and Microsystems
Volume22
Issue number7
DOIs
Publication statusPublished - 1999

Keywords

  • Cache-only memory architecture
  • Coherence protocol
  • Memory replacement
  • Shared bus

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications
  • Artificial Intelligence

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