Differential Pass Transistor Pulsed Latch

Mooyoung Kim, Inhwa Jung, Youngho Kwak, Sunghoon Ahn, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduce power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors enhance the speed of the latch as well as guarantee the full-swing of internal nodes. Also, the power consumption of proposed pulsed latch is reduced significantly due to the reduced clock load and smaller total transistor width compared to conventional differential flip-flops. DPTPL reduces ExD by 42.1% over modified-SAFF. The simulations were performed in a 0.13um CMOS technology at 1.2V supply voltage with 1.25GHz clock frequency.

Original languageEnglish
Title of host publicationProceedings - IEEE International SOC Conference, 2005 SOCC
EditorsD. Ha, R. Krishnamurthy, S. Kim, A. Marshall
Pages297-300
Number of pages4
Publication statusPublished - 2005
Event2005 IEEE International SOC Conference - Herndon, VA, United States
Duration: 2005 Sep 252005 Sep 28

Publication series

NameProceedings - IEEE International SOC Conference

Other

Other2005 IEEE International SOC Conference
CountryUnited States
CityHerndon, VA
Period05/9/2505/9/28

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Kim, M., Jung, I., Kwak, Y., Ahn, S., & Kim, C. (2005). Differential Pass Transistor Pulsed Latch. In D. Ha, R. Krishnamurthy, S. Kim, & A. Marshall (Eds.), Proceedings - IEEE International SOC Conference, 2005 SOCC (pp. 297-300). [WB3.1] (Proceedings - IEEE International SOC Conference).