Distance-aware L2 cache organizations for scalable multiprocessor systems

Sung Woo Jung, Hyong Shik Kim, Chu Shik Jhon

Research output: Contribution to journalArticle

Abstract

In order to provide the scalability to the multiprocessor systems, it is important to keep the remote memory access time in bounds so that it does not impose much additional overhead as the system grows. In this paper, we suggest an LRU/distance-aware combined second-level(L2) cache for scalable CC-NUMA multiprocessors, which is composed of a traditional LRU cache and an additional distance-aware cache that maintains the distance information of individual cache block for replacement purposes. The LRU cache selects a victim using age information as it typically does, while the distance-aware cache does using distance information. Both work together to reduce effectively the overall distance the cache miss goes through by keeping long-distance blocks as well as recently used blocks. It has been observed that the proposed cache outperforms the traditional LRU cache by up to 28% in the execution time. It is also found to perform even better than an LRU cache of twice the size.

Original languageEnglish
Pages (from-to)368-381
Number of pages14
JournalJournal of Systems Architecture
Volume51
Issue number6-7
DOIs
Publication statusPublished - 2005 Jun 1
Externally publishedYes

Fingerprint

Scalability
Data storage equipment

Keywords

  • Cache replacement policy
  • CC-NUMA
  • Distance-awareness
  • L2 cache organization
  • Scalable multiprocessor systems

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software

Cite this

Distance-aware L2 cache organizations for scalable multiprocessor systems. / Jung, Sung Woo; Kim, Hyong Shik; Jhon, Chu Shik.

In: Journal of Systems Architecture, Vol. 51, No. 6-7, 01.06.2005, p. 368-381.

Research output: Contribution to journalArticle

Jung, Sung Woo ; Kim, Hyong Shik ; Jhon, Chu Shik. / Distance-aware L2 cache organizations for scalable multiprocessor systems. In: Journal of Systems Architecture. 2005 ; Vol. 51, No. 6-7. pp. 368-381.
@article{609b729491b442739f2d305a4bbd4e4b,
title = "Distance-aware L2 cache organizations for scalable multiprocessor systems",
abstract = "In order to provide the scalability to the multiprocessor systems, it is important to keep the remote memory access time in bounds so that it does not impose much additional overhead as the system grows. In this paper, we suggest an LRU/distance-aware combined second-level(L2) cache for scalable CC-NUMA multiprocessors, which is composed of a traditional LRU cache and an additional distance-aware cache that maintains the distance information of individual cache block for replacement purposes. The LRU cache selects a victim using age information as it typically does, while the distance-aware cache does using distance information. Both work together to reduce effectively the overall distance the cache miss goes through by keeping long-distance blocks as well as recently used blocks. It has been observed that the proposed cache outperforms the traditional LRU cache by up to 28{\%} in the execution time. It is also found to perform even better than an LRU cache of twice the size.",
keywords = "Cache replacement policy, CC-NUMA, Distance-awareness, L2 cache organization, Scalable multiprocessor systems",
author = "Jung, {Sung Woo} and Kim, {Hyong Shik} and Jhon, {Chu Shik}",
year = "2005",
month = "6",
day = "1",
doi = "10.1016/j.sysarc.2004.07.006",
language = "English",
volume = "51",
pages = "368--381",
journal = "Journal of Systems Architecture",
issn = "1383-7621",
publisher = "Elsevier",
number = "6-7",

}

TY - JOUR

T1 - Distance-aware L2 cache organizations for scalable multiprocessor systems

AU - Jung, Sung Woo

AU - Kim, Hyong Shik

AU - Jhon, Chu Shik

PY - 2005/6/1

Y1 - 2005/6/1

N2 - In order to provide the scalability to the multiprocessor systems, it is important to keep the remote memory access time in bounds so that it does not impose much additional overhead as the system grows. In this paper, we suggest an LRU/distance-aware combined second-level(L2) cache for scalable CC-NUMA multiprocessors, which is composed of a traditional LRU cache and an additional distance-aware cache that maintains the distance information of individual cache block for replacement purposes. The LRU cache selects a victim using age information as it typically does, while the distance-aware cache does using distance information. Both work together to reduce effectively the overall distance the cache miss goes through by keeping long-distance blocks as well as recently used blocks. It has been observed that the proposed cache outperforms the traditional LRU cache by up to 28% in the execution time. It is also found to perform even better than an LRU cache of twice the size.

AB - In order to provide the scalability to the multiprocessor systems, it is important to keep the remote memory access time in bounds so that it does not impose much additional overhead as the system grows. In this paper, we suggest an LRU/distance-aware combined second-level(L2) cache for scalable CC-NUMA multiprocessors, which is composed of a traditional LRU cache and an additional distance-aware cache that maintains the distance information of individual cache block for replacement purposes. The LRU cache selects a victim using age information as it typically does, while the distance-aware cache does using distance information. Both work together to reduce effectively the overall distance the cache miss goes through by keeping long-distance blocks as well as recently used blocks. It has been observed that the proposed cache outperforms the traditional LRU cache by up to 28% in the execution time. It is also found to perform even better than an LRU cache of twice the size.

KW - Cache replacement policy

KW - CC-NUMA

KW - Distance-awareness

KW - L2 cache organization

KW - Scalable multiprocessor systems

UR - http://www.scopus.com/inward/record.url?scp=19744369921&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=19744369921&partnerID=8YFLogxK

U2 - 10.1016/j.sysarc.2004.07.006

DO - 10.1016/j.sysarc.2004.07.006

M3 - Article

AN - SCOPUS:19744369921

VL - 51

SP - 368

EP - 381

JO - Journal of Systems Architecture

JF - Journal of Systems Architecture

SN - 1383-7621

IS - 6-7

ER -