In high-speed data transmission applications such as double data rate memory and double sampling ADCs, clock generation and distribution circuits must provide the clocks with precise duty cycle of 50% and sufficient timing margin. The proposed DLL-based 4-phase duty-cycle and phase correction circuit, consisting of delay-locked loop (DLL) and 45 phase clock generator (SR latch) corrects distorted duty-cycle clock to 50% duty-cycle. The distorted duty-cycle input clock passes through the DLL. After the DLL is locked, the delay of delay line is identical to the period of input clock. Lastly, 4-phase, 50% duty-cycle clocks is generated from the combination of rising edges of signals at each 1/4 points of delay line. The proposed circuit is implemented in 65nm CMOS. The simulation results shows that the frequency range of the proposed circuits is 550-1600MHz, the maximum duty cycle error of the output clock can be less than 1% with the input duty cycle correction ranging from 25% to 80%. The phase difference with the 4-phase output clock is 250±3ps at a frequency of 1GHz. The measured power dissipation is 4.3mW.
|Journal||MATEC Web of Conferences|
|Publication status||Published - 2016 Apr 22|
|Event||2016 7th International Conference on Mechanical, Industrial, and Manufacturing Technologies, MIMT 2016 - Cape Town, South Africa|
Duration: 2016 Feb 1 → 2016 Feb 3
ASJC Scopus subject areas
- Materials Science(all)