Domain Wall Memory based Digital Signal processors for area and energy-efficiency

Jinil Chung, Kenneth Ramclam, Jongsun Park, Swaroop Ghosh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In many Digital Signal Processing (DSP) applications such as Viterbi decoder and Fast Fourier Transform (FFT), Static Random Access Memory (SRAM) based embedded memory consumes significant portion of area and power. These DSP units are dominated by sequential memory access where SRAM-based memory is inefficient in terms of area and power. We propose spintronic Domain Wall Memory (DWM) based embedded memories for DSP building blocks e.g., survivor-path memories in Viterbi decoder and First-In-First-Out (FIFO) register files in FFT processor that exploit the unique serial access mechanism, non-volatility and small footprint of the memory for area and power saving. Simulations using 65nm technology show that the DWM based Viterbi decoder achieves 66.4 % area and 59.6 % power savings over the conventional SRAM-based implementation. For 8K point FFT processor, the DWM based design shows 60.6 % area and 60.3 % power savings.

Original languageEnglish
Title of host publicationProceedings - Design Automation Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Volume2015-July
ISBN (Print)9781450335201
DOIs
Publication statusPublished - 2015 Jul 24
Event52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015 - San Francisco, United States
Duration: 2015 Jun 82015 Jun 12

Other

Other52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015
CountryUnited States
CitySan Francisco
Period15/6/815/6/12

Fingerprint

Digital Signal Processor
Domain walls
Domain Wall
Digital signal processors
Energy Efficiency
Energy efficiency
Data storage equipment
Power Saving
Random Access
Fast Fourier transform
Digital signal processing
Fast Fourier transforms
Signal Processing
Spintronics
Magnetoelectronics
Building Blocks

Keywords

  • Digital Signal Processor
  • Domain Wall Memory
  • Embedded Memory
  • STT-MRAM

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modelling and Simulation

Cite this

Chung, J., Ramclam, K., Park, J., & Ghosh, S. (2015). Domain Wall Memory based Digital Signal processors for area and energy-efficiency. In Proceedings - Design Automation Conference (Vol. 2015-July). [7167248] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/2744769.2744825

Domain Wall Memory based Digital Signal processors for area and energy-efficiency. / Chung, Jinil; Ramclam, Kenneth; Park, Jongsun; Ghosh, Swaroop.

Proceedings - Design Automation Conference. Vol. 2015-July Institute of Electrical and Electronics Engineers Inc., 2015. 7167248.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chung, J, Ramclam, K, Park, J & Ghosh, S 2015, Domain Wall Memory based Digital Signal processors for area and energy-efficiency. in Proceedings - Design Automation Conference. vol. 2015-July, 7167248, Institute of Electrical and Electronics Engineers Inc., 52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015, San Francisco, United States, 15/6/8. https://doi.org/10.1145/2744769.2744825
Chung J, Ramclam K, Park J, Ghosh S. Domain Wall Memory based Digital Signal processors for area and energy-efficiency. In Proceedings - Design Automation Conference. Vol. 2015-July. Institute of Electrical and Electronics Engineers Inc. 2015. 7167248 https://doi.org/10.1145/2744769.2744825
Chung, Jinil ; Ramclam, Kenneth ; Park, Jongsun ; Ghosh, Swaroop. / Domain Wall Memory based Digital Signal processors for area and energy-efficiency. Proceedings - Design Automation Conference. Vol. 2015-July Institute of Electrical and Electronics Engineers Inc., 2015.
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