DRACO: Optimized CC-NUMA system with novel dual-link interconnections to reduce the memory latency

Hyo Joong Suh; Sung Woo Chung

doi:10.1145/1152922.1101872

DRACO: Optimized CC-NUMA system with novel dual-link interconnections to reduce the memory latency

Hyo Joong Suh, Sung Woo Chung

Research output: Contribution to conference › Paper › peer-review

1 Citation (Scopus)

Abstract

The performances of multiprocessor systems mainly rely on the processor clock speed and the memory latency. As the processors speed up rapidly, the memory latency becomes a major performance bottleneck in multiprocessor systems. In this paper, we propose a dual-link interconnection topology and its effective routing scheme to reduce the remote memory latency on the interconnection network. It can be applied at a same implementation cost as traditional bi-directional ring systems. We compare the performance of the proposed system to that of the traditional bi-directional ring-based system and toroidal mesh-based system. By simulations, it is shown that the proposed system outperforms the traditional bi-directional ring-based system by 42∼101 % and excels the toroidal mesh-based system by 4∼14%.

Original language	English
Pages	10-16
Number of pages	7
DOIs	https://doi.org/10.1145/1152922.1101872
Publication status	Published - 2004
Externally published	Yes
Event	2004 Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '04 - Antibes Juan-les-Pins, France Duration: 2004 Sept 29 → 2004 Oct 3

Other

Other	2004 Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '04
Country/Territory	France
City	Antibes Juan-les-Pins
Period	04/9/29 → 04/10/3

ASJC Scopus subject areas

Computer Science Applications
Hardware and Architecture
Electrical and Electronic Engineering

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10.1145/1152922.1101872

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@conference{a902b1f0e590418fa0c787d4fd32cc20,

title = "DRACO: Optimized CC-NUMA system with novel dual-link interconnections to reduce the memory latency",

abstract = "The performances of multiprocessor systems mainly rely on the processor clock speed and the memory latency. As the processors speed up rapidly, the memory latency becomes a major performance bottleneck in multiprocessor systems. In this paper, we propose a dual-link interconnection topology and its effective routing scheme to reduce the remote memory latency on the interconnection network. It can be applied at a same implementation cost as traditional bi-directional ring systems. We compare the performance of the proposed system to that of the traditional bi-directional ring-based system and toroidal mesh-based system. By simulations, it is shown that the proposed system outperforms the traditional bi-directional ring-based system by 42∼101 % and excels the toroidal mesh-based system by 4∼14%.",

author = "Suh, {Hyo Joong} and Chung, {Sung Woo}",

year = "2004",

doi = "10.1145/1152922.1101872",

language = "English",

pages = "10--16",

note = "2004 Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '04 ; Conference date: 29-09-2004 Through 03-10-2004",

}

TY - CONF

T1 - DRACO

T2 - 2004 Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '04

AU - Suh, Hyo Joong

AU - Chung, Sung Woo

PY - 2004

Y1 - 2004

N2 - The performances of multiprocessor systems mainly rely on the processor clock speed and the memory latency. As the processors speed up rapidly, the memory latency becomes a major performance bottleneck in multiprocessor systems. In this paper, we propose a dual-link interconnection topology and its effective routing scheme to reduce the remote memory latency on the interconnection network. It can be applied at a same implementation cost as traditional bi-directional ring systems. We compare the performance of the proposed system to that of the traditional bi-directional ring-based system and toroidal mesh-based system. By simulations, it is shown that the proposed system outperforms the traditional bi-directional ring-based system by 42∼101 % and excels the toroidal mesh-based system by 4∼14%.

AB - The performances of multiprocessor systems mainly rely on the processor clock speed and the memory latency. As the processors speed up rapidly, the memory latency becomes a major performance bottleneck in multiprocessor systems. In this paper, we propose a dual-link interconnection topology and its effective routing scheme to reduce the remote memory latency on the interconnection network. It can be applied at a same implementation cost as traditional bi-directional ring systems. We compare the performance of the proposed system to that of the traditional bi-directional ring-based system and toroidal mesh-based system. By simulations, it is shown that the proposed system outperforms the traditional bi-directional ring-based system by 42∼101 % and excels the toroidal mesh-based system by 4∼14%.

UR - http://www.scopus.com/inward/record.url?scp=77953501402&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77953501402&partnerID=8YFLogxK

U2 - 10.1145/1152922.1101872

DO - 10.1145/1152922.1101872

M3 - Paper

AN - SCOPUS:77953501402

SP - 10

EP - 16

Y2 - 29 September 2004 through 3 October 2004

ER -

DRACO: Optimized CC-NUMA system with novel dual-link interconnections to reduce the memory latency

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