Dynamic partition of memory reference instructions - A register guided approach

Yixin Shi, Gyungho Lee

Research output: Contribution to journalConference articlepeer-review

1 Citation (Scopus)

Abstract

A high bandwidth L-1 data cache is essential for achieving high performance in wide-issue processors. Previous studies have shown that using multiple small single-ported caches instead of a monolithic large multi-ported one for L-1 data cache can be a scalable and inexpensive way to provide higher bandwidth. Many schemes have been proposed on how to direct the memory references to these multiple caches in order to achieve a close match to the performance of an ideal multi-ported cache. However, most previous designs seldom take dynamic data access patterns into consideration and thus suffer from access conflicts within one cache and unbalanced loads between the caches. We observe that if one can group data references defined in a program into several regions (access regions) to allow parallel accesses, then providing separate small caches (access region cache) for these regions may prove to have better performance than previous multi-cache schemes. The register-guided memory reference partition approach proposed in this paper effectively identifies these semantic regions and organizes them in multiple caches in an adaptive way to maximize concurrent accesses without incurring too much overhead. In our design, the base register number, not its content, in the memory reference instruction is used as a basic guide for instruction steering. A reassignment mechanism is applied to capture the pattern when program is moving across its access regions. In addition, a distribution mechanism is introduced to further reduce residual conflicts, which adaptively enables access regions to extend or shrink among the physical caches. Our simulations of SPEC CPU2000 benchmarks have shown that the register-guided approach can reduce the conflicts effectively, distribute memory reference instructions properly, and yield considerable performance improvement in terms of IPC.

Original languageEnglish
Pages (from-to)508-518
Number of pages11
JournalLecture Notes in Computer Science
Volume3648
DOIs
Publication statusPublished - 2005
Externally publishedYes
Event11th International Euro-Par Conference, Euro-Par 2005 - Lisbon, Portugal
Duration: 2005 Aug 302005 Sep 2

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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