TY - JOUR
T1 - Edge-Pursuit Comparator
T2 - An Energy-Scalable Oscillator Collapse-Based Comparator with Application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC
AU - Shim, Minseob
AU - Jeong, Seokhyeon
AU - Myers, Paul D.
AU - Bang, Suyoung
AU - Shen, Junhua
AU - Kim, Chulwoo
AU - Sylvester, Dennis
AU - Blaauw, David
AU - Jung, Wanyeong
PY - 2017/4
Y1 - 2017/4
N2 - This paper presents a new energy-efficient ring oscillator collapse-based comparator, named edge-pursuit comparator (EPC). This comparator automatically adjusts the performance by changing the comparison energy according to its input difference without any control, eliminating unnecessary energy spent on coarse comparisons. Furthermore, a detailed analysis of the EPC in the phase domain shows improved energy efficiency over conventional comparators even without energy scaling, and wider resolution tuning capability with small load capacitance and area. The EPC is used in a successive-approximation-register analog-to-digital converter (SAR ADC) design, which supplements a 10 b differential coarse capacitive digital-to-analog converter (CDAC) with a 5 b common-mode CDAC. This offers an additional 5 b of resolution with common mode to differential gain tuning that improves linearity by reducing the effect of switch parasitic capacitance. A test chip fabricated in 40 nm CMOS shows 74.12 dB signal-to-noise and distortion ratio and 173.4 dB Schreier Figure-of-Merit. With the full ADC consuming 1.17 μW, the comparator consumes 104 nW, which is only 8.9% of the full ADC power, proving the comparator's energy efficiency.
AB - This paper presents a new energy-efficient ring oscillator collapse-based comparator, named edge-pursuit comparator (EPC). This comparator automatically adjusts the performance by changing the comparison energy according to its input difference without any control, eliminating unnecessary energy spent on coarse comparisons. Furthermore, a detailed analysis of the EPC in the phase domain shows improved energy efficiency over conventional comparators even without energy scaling, and wider resolution tuning capability with small load capacitance and area. The EPC is used in a successive-approximation-register analog-to-digital converter (SAR ADC) design, which supplements a 10 b differential coarse capacitive digital-to-analog converter (CDAC) with a 5 b common-mode CDAC. This offers an additional 5 b of resolution with common mode to differential gain tuning that improves linearity by reducing the effect of switch parasitic capacitance. A test chip fabricated in 40 nm CMOS shows 74.12 dB signal-to-noise and distortion ratio and 173.4 dB Schreier Figure-of-Merit. With the full ADC consuming 1.17 μW, the comparator consumes 104 nW, which is only 8.9% of the full ADC power, proving the comparator's energy efficiency.
KW - Common-mode CDAC
KW - SAR ADC
KW - edge-pursuit comparator (EPC)
KW - high-resolution ADC
KW - noise analysis
KW - oscillator collapse
KW - phase domain
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U2 - 10.1109/JSSC.2016.2631299
DO - 10.1109/JSSC.2016.2631299
M3 - Article
AN - SCOPUS:85009876169
VL - 52
SP - 1077
EP - 1090
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 4
M1 - 7815388
ER -