Effective instruction fetch stage design for 16-bit instruction set architecture

Kim Areum, Joong Hwang Seok, Seon Wook Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The 16-bit instruction set architecture has merits in terms of code size reduction and instruction cache efficiency. But we have taken the advantages at the cost of performance due to lack of an available expression space for a long immediate value, a three-address mode and so on. This paper presents a new instruction coalescing technique named as move folding to remove redundant move instructions caused by the limitation of the 16-bit instruction set. We prove effectiveness of the technique by implementing it on a commercial microprocessor. The proposed move folding technique improves speedup of 5% on average and up to 18% at the cost of 4.3% hardware complexity increment.

Original languageEnglish
Title of host publicationProceedings - 8th IEEE International Conference on Computer and Information Technology Workshops, CIT Workshops 2008
Pages563-568
Number of pages6
DOIs
Publication statusPublished - 2008 Sep 24
Event8th IEEE International Conference on Computer and Information Technology Workshops, CIT Workshops 2008 - Sydney, Australia
Duration: 2008 Jul 82008 Jul 11

Other

Other8th IEEE International Conference on Computer and Information Technology Workshops, CIT Workshops 2008
CountryAustralia
CitySydney
Period08/7/808/7/11

Fingerprint

Microprocessor chips
Hardware

ASJC Scopus subject areas

  • Computer Science(all)
  • Computer Graphics and Computer-Aided Design
  • Information Systems
  • Electrical and Electronic Engineering

Cite this

Areum, K., Seok, J. H., & Kim, S. W. (2008). Effective instruction fetch stage design for 16-bit instruction set architecture. In Proceedings - 8th IEEE International Conference on Computer and Information Technology Workshops, CIT Workshops 2008 (pp. 563-568). [4568564] https://doi.org/10.1109/CIT.2008.Workshops.107

Effective instruction fetch stage design for 16-bit instruction set architecture. / Areum, Kim; Seok, Joong Hwang; Kim, Seon Wook.

Proceedings - 8th IEEE International Conference on Computer and Information Technology Workshops, CIT Workshops 2008. 2008. p. 563-568 4568564.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Areum, K, Seok, JH & Kim, SW 2008, Effective instruction fetch stage design for 16-bit instruction set architecture. in Proceedings - 8th IEEE International Conference on Computer and Information Technology Workshops, CIT Workshops 2008., 4568564, pp. 563-568, 8th IEEE International Conference on Computer and Information Technology Workshops, CIT Workshops 2008, Sydney, Australia, 08/7/8. https://doi.org/10.1109/CIT.2008.Workshops.107
Areum K, Seok JH, Kim SW. Effective instruction fetch stage design for 16-bit instruction set architecture. In Proceedings - 8th IEEE International Conference on Computer and Information Technology Workshops, CIT Workshops 2008. 2008. p. 563-568. 4568564 https://doi.org/10.1109/CIT.2008.Workshops.107
Areum, Kim ; Seok, Joong Hwang ; Kim, Seon Wook. / Effective instruction fetch stage design for 16-bit instruction set architecture. Proceedings - 8th IEEE International Conference on Computer and Information Technology Workshops, CIT Workshops 2008. 2008. pp. 563-568
@inproceedings{606fac5bde8f494f823665639537537f,
title = "Effective instruction fetch stage design for 16-bit instruction set architecture",
abstract = "The 16-bit instruction set architecture has merits in terms of code size reduction and instruction cache efficiency. But we have taken the advantages at the cost of performance due to lack of an available expression space for a long immediate value, a three-address mode and so on. This paper presents a new instruction coalescing technique named as move folding to remove redundant move instructions caused by the limitation of the 16-bit instruction set. We prove effectiveness of the technique by implementing it on a commercial microprocessor. The proposed move folding technique improves speedup of 5{\%} on average and up to 18{\%} at the cost of 4.3{\%} hardware complexity increment.",
author = "Kim Areum and Seok, {Joong Hwang} and Kim, {Seon Wook}",
year = "2008",
month = "9",
day = "24",
doi = "10.1109/CIT.2008.Workshops.107",
language = "English",
isbn = "9780769533391",
pages = "563--568",
booktitle = "Proceedings - 8th IEEE International Conference on Computer and Information Technology Workshops, CIT Workshops 2008",

}

TY - GEN

T1 - Effective instruction fetch stage design for 16-bit instruction set architecture

AU - Areum, Kim

AU - Seok, Joong Hwang

AU - Kim, Seon Wook

PY - 2008/9/24

Y1 - 2008/9/24

N2 - The 16-bit instruction set architecture has merits in terms of code size reduction and instruction cache efficiency. But we have taken the advantages at the cost of performance due to lack of an available expression space for a long immediate value, a three-address mode and so on. This paper presents a new instruction coalescing technique named as move folding to remove redundant move instructions caused by the limitation of the 16-bit instruction set. We prove effectiveness of the technique by implementing it on a commercial microprocessor. The proposed move folding technique improves speedup of 5% on average and up to 18% at the cost of 4.3% hardware complexity increment.

AB - The 16-bit instruction set architecture has merits in terms of code size reduction and instruction cache efficiency. But we have taken the advantages at the cost of performance due to lack of an available expression space for a long immediate value, a three-address mode and so on. This paper presents a new instruction coalescing technique named as move folding to remove redundant move instructions caused by the limitation of the 16-bit instruction set. We prove effectiveness of the technique by implementing it on a commercial microprocessor. The proposed move folding technique improves speedup of 5% on average and up to 18% at the cost of 4.3% hardware complexity increment.

UR - http://www.scopus.com/inward/record.url?scp=52049102050&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=52049102050&partnerID=8YFLogxK

U2 - 10.1109/CIT.2008.Workshops.107

DO - 10.1109/CIT.2008.Workshops.107

M3 - Conference contribution

AN - SCOPUS:52049102050

SN - 9780769533391

SP - 563

EP - 568

BT - Proceedings - 8th IEEE International Conference on Computer and Information Technology Workshops, CIT Workshops 2008

ER -