TY - JOUR
T1 - Effects of channel width variation on electrical characteristics of tri-gate Junctionless transistors
AU - Jeon, Dae Young
AU - Park, So Jeong
AU - Mouis, Mireille
AU - Barraud, Sylvain
AU - Kim, Gyu Tae
AU - Ghibaudo, Gérard
N1 - Funding Information:
This work was supported by European Union 7th Framework Program project SQWIRE under Grant agreement No. 257111 and by the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (Converging Research Center Program, 2012K001313 and Global Frontier Research Program, No. 2011-0031638).
PY - 2013
Y1 - 2013
N2 - The electrical behavior of tri-gate Junctionless transistors (JLTs) depending on top-effective width (Wtop-eff) was investigated, experimentally. As decreasing Wtop-eff, the amount of bulk neutral channel is relatively getting smaller than that of surface accumulation channel, whereas the channel sidewall gate effect is reinforced. These cause the shrinkage of the shoulder shape on the gate-to-channel capacitance characteristics (Cgc-Vg), resulting in a noticeable change in the effective mobility (μeff) behavior from that in wide JLT devices, an increase of the threshold voltage (Vth), while the flat-band voltage (Vfb) does not change. 2D numerical simulation results, well consistent to the experimental results, confirm the significant sidewall gate effect in the tri-gate JLT devices with a narrow structure.
AB - The electrical behavior of tri-gate Junctionless transistors (JLTs) depending on top-effective width (Wtop-eff) was investigated, experimentally. As decreasing Wtop-eff, the amount of bulk neutral channel is relatively getting smaller than that of surface accumulation channel, whereas the channel sidewall gate effect is reinforced. These cause the shrinkage of the shoulder shape on the gate-to-channel capacitance characteristics (Cgc-Vg), resulting in a noticeable change in the effective mobility (μeff) behavior from that in wide JLT devices, an increase of the threshold voltage (Vth), while the flat-band voltage (Vfb) does not change. 2D numerical simulation results, well consistent to the experimental results, confirm the significant sidewall gate effect in the tri-gate JLT devices with a narrow structure.
KW - 2D numerical simulation
KW - Effective mobility (μ)
KW - Effective width
KW - Flat-band voltage (V)
KW - Junctionless transistors (JLTs)
KW - Sidewall gate effect
KW - Threshold voltage (V)
UR - http://www.scopus.com/inward/record.url?scp=84874701134&partnerID=8YFLogxK
U2 - 10.1016/j.sse.2013.01.002
DO - 10.1016/j.sse.2013.01.002
M3 - Article
AN - SCOPUS:84874701134
SN - 0038-1101
VL - 81
SP - 58
EP - 62
JO - Solid-State Electronics
JF - Solid-State Electronics
ER -