This paper addresses the effects of design options on the cost and the performance of CMPs (chip multiprocessors) with a shared L2 cache. The design options we consider include the instruction-issue rates of the processors and the sizes of the internal caches. We focus our study more on implementation issues rather than architectural perspectives. We model all the functional blocks of the CMPs in hardware description language and estimate their cost/performance by using a program-driven simulator developed for this study. Realistic parameters for current technologies are used in the CPU/memory-system simulation models. Our results show that clustering four CPUs with single issue, integrating a 4-kbyte L1 cache and a 128-kbyte L2 cache, could be the best choice for the technologies considered.
|Number of pages||7|
|Journal||Journal of the Korean Physical Society|
|Publication status||Published - 2001 Jul|
ASJC Scopus subject areas
- Physics and Astronomy(all)