Effects of metal-interlayer-semiconductor source/drain contact structure on n-type germanium junctionless FinFETs

Seung Geun Jung, Seung Hwan Kim, Gwang Sik Kim, Hyun-Yong Yu

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

In this paper, the effects of a metal-interlayer-semiconductor (MIS) source/drain (S/D) structure with a heavily doped interlayer on enhancement-mode n-type germanium (Ge) junctionless FinFETs (JLFETs) are demonstrated via 3-D technology computer aided design simulation. N-type Ge JLFETs using metal-semiconductor (MS) S/D structures face difficulty in operating in the enhancement mode, as severe Fermi-level pinning (FLP) triggers extremely high off-state current (IOFF) and extremely low on-state current (ION). The MIS S/D structure can solve these problems by mitigating FLP. In the simulation of an n-type Ge JLFET with the MIS S/D structure, IOFF of 9.42 × 10-10 A/ μ m, ION of 6.09 × 10-4 A/ μ m, and subthreshold slope of 65.38 mV/dec are achieved. The performance of the device for different channel-doping concentrations and fin dimensions is also evaluated. Thus, an MIS S/D structure with a heavily doped interlayer can effectively strengthen the performances of n-type Ge JLFETs beyond the sub-7-nm technology node.

Original languageEnglish
Article number8401844
Pages (from-to)3136-3141
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume65
Issue number8
DOIs
Publication statusPublished - 2018 Aug 1

Keywords

  • 3-D technology computer aided design (TCAD) simulation
  • CMOS
  • germanium
  • interlayer
  • junctionless FET

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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