Effects of metal-interlayer-semiconductor source/drain contact structure on n-type germanium junctionless FinFETs

Seung Geun Jung, Seung Hwan Kim, Gwang Sik Kim, Hyun-Yong Yu

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

In this paper, the effects of a metal-interlayer-semiconductor (MIS) source/drain (S/D) structure with a heavily doped interlayer on enhancement-mode n-type germanium (Ge) junctionless FinFETs (JLFETs) are demonstrated via 3-D technology computer aided design simulation. N-type Ge JLFETs using metal-semiconductor (MS) S/D structures face difficulty in operating in the enhancement mode, as severe Fermi-level pinning (FLP) triggers extremely high off-state current (IOFF) and extremely low on-state current (ION). The MIS S/D structure can solve these problems by mitigating FLP. In the simulation of an n-type Ge JLFET with the MIS S/D structure, IOFF of 9.42 × 10-10 A/ μ m, ION of 6.09 × 10-4 A/ μ m, and subthreshold slope of 65.38 mV/dec are achieved. The performance of the device for different channel-doping concentrations and fin dimensions is also evaluated. Thus, an MIS S/D structure with a heavily doped interlayer can effectively strengthen the performances of n-type Ge JLFETs beyond the sub-7-nm technology node.

Original languageEnglish
Article number8401844
Pages (from-to)3136-3141
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume65
Issue number8
DOIs
Publication statusPublished - 2018 Aug 1

Fingerprint

Germanium
Metals
Semiconductor materials
Fermi level
Computer aided design
Doping (additives)
FinFET

Keywords

  • 3-D technology computer aided design (TCAD) simulation
  • CMOS
  • germanium
  • interlayer
  • junctionless FET

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Effects of metal-interlayer-semiconductor source/drain contact structure on n-type germanium junctionless FinFETs. / Jung, Seung Geun; Kim, Seung Hwan; Kim, Gwang Sik; Yu, Hyun-Yong.

In: IEEE Transactions on Electron Devices, Vol. 65, No. 8, 8401844, 01.08.2018, p. 3136-3141.

Research output: Contribution to journalArticle

@article{269edb8d9138401682e0839d96978417,
title = "Effects of metal-interlayer-semiconductor source/drain contact structure on n-type germanium junctionless FinFETs",
abstract = "In this paper, the effects of a metal-interlayer-semiconductor (MIS) source/drain (S/D) structure with a heavily doped interlayer on enhancement-mode n-type germanium (Ge) junctionless FinFETs (JLFETs) are demonstrated via 3-D technology computer aided design simulation. N-type Ge JLFETs using metal-semiconductor (MS) S/D structures face difficulty in operating in the enhancement mode, as severe Fermi-level pinning (FLP) triggers extremely high off-state current (IOFF) and extremely low on-state current (ION). The MIS S/D structure can solve these problems by mitigating FLP. In the simulation of an n-type Ge JLFET with the MIS S/D structure, IOFF of 9.42 × 10-10 A/ μ m, ION of 6.09 × 10-4 A/ μ m, and subthreshold slope of 65.38 mV/dec are achieved. The performance of the device for different channel-doping concentrations and fin dimensions is also evaluated. Thus, an MIS S/D structure with a heavily doped interlayer can effectively strengthen the performances of n-type Ge JLFETs beyond the sub-7-nm technology node.",
keywords = "3-D technology computer aided design (TCAD) simulation, CMOS, germanium, interlayer, junctionless FET",
author = "Jung, {Seung Geun} and Kim, {Seung Hwan} and Kim, {Gwang Sik} and Hyun-Yong Yu",
year = "2018",
month = "8",
day = "1",
doi = "10.1109/TED.2018.2847418",
language = "English",
volume = "65",
pages = "3136--3141",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "8",

}

TY - JOUR

T1 - Effects of metal-interlayer-semiconductor source/drain contact structure on n-type germanium junctionless FinFETs

AU - Jung, Seung Geun

AU - Kim, Seung Hwan

AU - Kim, Gwang Sik

AU - Yu, Hyun-Yong

PY - 2018/8/1

Y1 - 2018/8/1

N2 - In this paper, the effects of a metal-interlayer-semiconductor (MIS) source/drain (S/D) structure with a heavily doped interlayer on enhancement-mode n-type germanium (Ge) junctionless FinFETs (JLFETs) are demonstrated via 3-D technology computer aided design simulation. N-type Ge JLFETs using metal-semiconductor (MS) S/D structures face difficulty in operating in the enhancement mode, as severe Fermi-level pinning (FLP) triggers extremely high off-state current (IOFF) and extremely low on-state current (ION). The MIS S/D structure can solve these problems by mitigating FLP. In the simulation of an n-type Ge JLFET with the MIS S/D structure, IOFF of 9.42 × 10-10 A/ μ m, ION of 6.09 × 10-4 A/ μ m, and subthreshold slope of 65.38 mV/dec are achieved. The performance of the device for different channel-doping concentrations and fin dimensions is also evaluated. Thus, an MIS S/D structure with a heavily doped interlayer can effectively strengthen the performances of n-type Ge JLFETs beyond the sub-7-nm technology node.

AB - In this paper, the effects of a metal-interlayer-semiconductor (MIS) source/drain (S/D) structure with a heavily doped interlayer on enhancement-mode n-type germanium (Ge) junctionless FinFETs (JLFETs) are demonstrated via 3-D technology computer aided design simulation. N-type Ge JLFETs using metal-semiconductor (MS) S/D structures face difficulty in operating in the enhancement mode, as severe Fermi-level pinning (FLP) triggers extremely high off-state current (IOFF) and extremely low on-state current (ION). The MIS S/D structure can solve these problems by mitigating FLP. In the simulation of an n-type Ge JLFET with the MIS S/D structure, IOFF of 9.42 × 10-10 A/ μ m, ION of 6.09 × 10-4 A/ μ m, and subthreshold slope of 65.38 mV/dec are achieved. The performance of the device for different channel-doping concentrations and fin dimensions is also evaluated. Thus, an MIS S/D structure with a heavily doped interlayer can effectively strengthen the performances of n-type Ge JLFETs beyond the sub-7-nm technology node.

KW - 3-D technology computer aided design (TCAD) simulation

KW - CMOS

KW - germanium

KW - interlayer

KW - junctionless FET

UR - http://www.scopus.com/inward/record.url?scp=85049347144&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85049347144&partnerID=8YFLogxK

U2 - 10.1109/TED.2018.2847418

DO - 10.1109/TED.2018.2847418

M3 - Article

AN - SCOPUS:85049347144

VL - 65

SP - 3136

EP - 3141

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 8

M1 - 8401844

ER -