@article{269edb8d9138401682e0839d96978417,
title = "Effects of metal-interlayer-semiconductor source/drain contact structure on n-type germanium junctionless FinFETs",
abstract = "In this paper, the effects of a metal-interlayer-semiconductor (MIS) source/drain (S/D) structure with a heavily doped interlayer on enhancement-mode n-type germanium (Ge) junctionless FinFETs (JLFETs) are demonstrated via 3-D technology computer aided design simulation. N-type Ge JLFETs using metal-semiconductor (MS) S/D structures face difficulty in operating in the enhancement mode, as severe Fermi-level pinning (FLP) triggers extremely high off-state current (IOFF) and extremely low on-state current (ION). The MIS S/D structure can solve these problems by mitigating FLP. In the simulation of an n-type Ge JLFET with the MIS S/D structure, IOFF of 9.42 × 10-10 A/ μ m, ION of 6.09 × 10-4 A/ μ m, and subthreshold slope of 65.38 mV/dec are achieved. The performance of the device for different channel-doping concentrations and fin dimensions is also evaluated. Thus, an MIS S/D structure with a heavily doped interlayer can effectively strengthen the performances of n-type Ge JLFETs beyond the sub-7-nm technology node.",
keywords = "3-D technology computer aided design (TCAD) simulation, CMOS, germanium, interlayer, junctionless FET",
author = "Jung, {Seung Geun} and Kim, {Seung Hwan} and Kim, {Gwang Sik} and Yu, {Hyun Yong}",
note = "Funding Information: Manuscript received December 9, 2017; revised March 1, 2018 and May 1, 2018; accepted June 11, 2018. Date of publication July 2, 2018; date of current version July 23, 2018. This work was supported in part by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT, and Future Planning (2017R1A2B4006460) and in part by the Technology Innovation Program (10048594, Technology Development of Ge nMOS/pMOS FinFET for 10 nm Technology Node) funded by the Ministry of Trade, Industry & Energy (MI Korea) and the Nano Material Technology Development Program through the National Research Foundation of Korea Funded by the Ministry of Science, ICT and Future Planning under Grant 2015M3A7B7045490. The review of this paper was arranged by Editor H. Shang. (Corresponding author: Hyun-Yong Yu.) The authors are with the School of Electrical Engineering, Korea University, Seoul 02841, South Korea (e-mail: yuhykr@korea.ac.kr). Funding Information: The EDA tool was supported by the IC Design Education Center (IDEC), Daejeon, South Korea. Publisher Copyright: {\textcopyright} 1963-2012 IEEE. Copyright: Copyright 2018 Elsevier B.V., All rights reserved.",
year = "2018",
month = aug,
doi = "10.1109/TED.2018.2847418",
language = "English",
volume = "65",
pages = "3136--3141",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "8",
}