Efficient characterization and suppression methodology of edge effects for leakage current reduction of sub-40nm DRAM device

Han Choi Soo, Hee Park Young, Hong Park Chul, Hoon Lee Sang, Hyun Yoo Moon, Gyu-Tae Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

With the process scaling, the leakage current reduction has been the primary design concerns in a nanometer-era VLSI circuit. In this paper, we propose a new lithography process-aware edge effects correction method to reduce the leakage current in the shallow trench isolation (STI). We construct the various test structures to model Ileakage and I leakage-fringe which represent the leakage currents at the center and edge of the transistor, respectively. The layout near the active edge is modified using the look-up table generated by the calibrated analytic model. On average, the proposed edge effects correction method reduces the leakage current by 18% with the negligible decrease of the drive current at sub-40nm DRAM device.

Original languageEnglish
Title of host publicationIEEE International Conference on Microelectronic Test Structures
Pages34-37
Number of pages4
DOIs
Publication statusPublished - 2010 Jun 29
Event2010 International Conference on Microelectronic Test Structures, ICMTS 2010 - Hiroshima, Japan
Duration: 2010 Mar 222010 Mar 25

Other

Other2010 International Conference on Microelectronic Test Structures, ICMTS 2010
CountryJapan
CityHiroshima
Period10/3/2210/3/25

Fingerprint

Dynamic random access storage
Leakage currents
VLSI circuits
Lithography
Transistors

Keywords

  • Analytic model
  • Edge effects
  • Leakage current
  • Shaping gate channel

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Soo, H. C., Young, H. P., Chul, H. P., Sang, H. L., Moon, H. Y., & Kim, G-T. (2010). Efficient characterization and suppression methodology of edge effects for leakage current reduction of sub-40nm DRAM device. In IEEE International Conference on Microelectronic Test Structures (pp. 34-37). [5466864] https://doi.org/10.1109/ICMTS.2010.5466864

Efficient characterization and suppression methodology of edge effects for leakage current reduction of sub-40nm DRAM device. / Soo, Han Choi; Young, Hee Park; Chul, Hong Park; Sang, Hoon Lee; Moon, Hyun Yoo; Kim, Gyu-Tae.

IEEE International Conference on Microelectronic Test Structures. 2010. p. 34-37 5466864.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Soo, HC, Young, HP, Chul, HP, Sang, HL, Moon, HY & Kim, G-T 2010, Efficient characterization and suppression methodology of edge effects for leakage current reduction of sub-40nm DRAM device. in IEEE International Conference on Microelectronic Test Structures., 5466864, pp. 34-37, 2010 International Conference on Microelectronic Test Structures, ICMTS 2010, Hiroshima, Japan, 10/3/22. https://doi.org/10.1109/ICMTS.2010.5466864
Soo HC, Young HP, Chul HP, Sang HL, Moon HY, Kim G-T. Efficient characterization and suppression methodology of edge effects for leakage current reduction of sub-40nm DRAM device. In IEEE International Conference on Microelectronic Test Structures. 2010. p. 34-37. 5466864 https://doi.org/10.1109/ICMTS.2010.5466864
Soo, Han Choi ; Young, Hee Park ; Chul, Hong Park ; Sang, Hoon Lee ; Moon, Hyun Yoo ; Kim, Gyu-Tae. / Efficient characterization and suppression methodology of edge effects for leakage current reduction of sub-40nm DRAM device. IEEE International Conference on Microelectronic Test Structures. 2010. pp. 34-37
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