This paper presents an efficient discrete-time bandpass sigma-delta (∑Δ) modulator and digital in-phase/quadrature (I/Q) demodulator for multistandard wireless applications. The proposed bandpass ∑Δ modulator provides higher speed using advanced switched-capacitor resonators which are faster than the conventional ones. The test chip has been implemented in a 0.18 μm CMOS process and occupied with the active chip area of 0.16 mm2. The power consumption of the fabricated chip is 2.34 mW with a 1.8 V supply voltage. The measured peak signal-to-noise ratios (SNR) are 34 dB for 1.536 MHz (T-DMB), 26 dB for 5 MHz (UMTS), and 20 dB for 10 MHz (WiBro) bandwidths, respectively. This paper also covers the simple and robust digital I/Q demodulator which has been realized using a field programmable gate array (FPGA) for digital signal processing.
- Digital demodulator
- Sigma-delta modulation
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Computer Networks and Communications