Efficient sequential architecture for the AES CCM mode in the 802.16e standard

Jae Deok Ji, Seok Won Jung, Eun A. Jun, Jong In Lim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

We propose hardware architecture of the advanced encryption standard counter with the cipher block chaining-message authentication code (AES CCM) in the 802.16e standard. It has only one AES encryption core with composite field logic for SBOX. The logic is divided into two parts to perform one round at two clock cycles. In the proposed architecture, the counter (CTR) and the cipher block chaining-message authentication code (CBC-MAC) operations are processed in a sequential mode and share one AES encryption resource at the same time. The throughput of our design is about 588Mbps at 105MHz frequency with reasonable area requirements.

Original languageEnglish
Title of host publicationICINIS 2009 - Proceedings of the 2nd International Conference on Intelligent Networks and Intelligent Systems
Pages253-256
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
Event2nd International Conference on Intelligent Networks and Intelligent Systems, ICINIS 2009 - Tianjin, China
Duration: 2009 Nov 12009 Nov 3

Other

Other2nd International Conference on Intelligent Networks and Intelligent Systems, ICINIS 2009
CountryChina
CityTianjin
Period09/11/109/11/3

Fingerprint

Cryptography
Authentication
Computer hardware
Clocks
Throughput
Composite materials

Keywords

  • 802.16e
  • AES CCM
  • FPGA
  • SBOX composite logic

ASJC Scopus subject areas

  • Artificial Intelligence
  • Computer Networks and Communications
  • Information Systems
  • Software

Cite this

Ji, J. D., Jung, S. W., Jun, E. A., & Lim, J. I. (2009). Efficient sequential architecture for the AES CCM mode in the 802.16e standard. In ICINIS 2009 - Proceedings of the 2nd International Conference on Intelligent Networks and Intelligent Systems (pp. 253-256). [5364531] https://doi.org/10.1109/ICINIS.2009.71

Efficient sequential architecture for the AES CCM mode in the 802.16e standard. / Ji, Jae Deok; Jung, Seok Won; Jun, Eun A.; Lim, Jong In.

ICINIS 2009 - Proceedings of the 2nd International Conference on Intelligent Networks and Intelligent Systems. 2009. p. 253-256 5364531.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ji, JD, Jung, SW, Jun, EA & Lim, JI 2009, Efficient sequential architecture for the AES CCM mode in the 802.16e standard. in ICINIS 2009 - Proceedings of the 2nd International Conference on Intelligent Networks and Intelligent Systems., 5364531, pp. 253-256, 2nd International Conference on Intelligent Networks and Intelligent Systems, ICINIS 2009, Tianjin, China, 09/11/1. https://doi.org/10.1109/ICINIS.2009.71
Ji JD, Jung SW, Jun EA, Lim JI. Efficient sequential architecture for the AES CCM mode in the 802.16e standard. In ICINIS 2009 - Proceedings of the 2nd International Conference on Intelligent Networks and Intelligent Systems. 2009. p. 253-256. 5364531 https://doi.org/10.1109/ICINIS.2009.71
Ji, Jae Deok ; Jung, Seok Won ; Jun, Eun A. ; Lim, Jong In. / Efficient sequential architecture for the AES CCM mode in the 802.16e standard. ICINIS 2009 - Proceedings of the 2nd International Conference on Intelligent Networks and Intelligent Systems. 2009. pp. 253-256
@inproceedings{9ec10c042f0e4ea085919949287dbd49,
title = "Efficient sequential architecture for the AES CCM mode in the 802.16e standard",
abstract = "We propose hardware architecture of the advanced encryption standard counter with the cipher block chaining-message authentication code (AES CCM) in the 802.16e standard. It has only one AES encryption core with composite field logic for SBOX. The logic is divided into two parts to perform one round at two clock cycles. In the proposed architecture, the counter (CTR) and the cipher block chaining-message authentication code (CBC-MAC) operations are processed in a sequential mode and share one AES encryption resource at the same time. The throughput of our design is about 588Mbps at 105MHz frequency with reasonable area requirements.",
keywords = "802.16e, AES CCM, FPGA, SBOX composite logic",
author = "Ji, {Jae Deok} and Jung, {Seok Won} and Jun, {Eun A.} and Lim, {Jong In}",
year = "2009",
month = "12",
day = "1",
doi = "10.1109/ICINIS.2009.71",
language = "English",
isbn = "9780769538525",
pages = "253--256",
booktitle = "ICINIS 2009 - Proceedings of the 2nd International Conference on Intelligent Networks and Intelligent Systems",

}

TY - GEN

T1 - Efficient sequential architecture for the AES CCM mode in the 802.16e standard

AU - Ji, Jae Deok

AU - Jung, Seok Won

AU - Jun, Eun A.

AU - Lim, Jong In

PY - 2009/12/1

Y1 - 2009/12/1

N2 - We propose hardware architecture of the advanced encryption standard counter with the cipher block chaining-message authentication code (AES CCM) in the 802.16e standard. It has only one AES encryption core with composite field logic for SBOX. The logic is divided into two parts to perform one round at two clock cycles. In the proposed architecture, the counter (CTR) and the cipher block chaining-message authentication code (CBC-MAC) operations are processed in a sequential mode and share one AES encryption resource at the same time. The throughput of our design is about 588Mbps at 105MHz frequency with reasonable area requirements.

AB - We propose hardware architecture of the advanced encryption standard counter with the cipher block chaining-message authentication code (AES CCM) in the 802.16e standard. It has only one AES encryption core with composite field logic for SBOX. The logic is divided into two parts to perform one round at two clock cycles. In the proposed architecture, the counter (CTR) and the cipher block chaining-message authentication code (CBC-MAC) operations are processed in a sequential mode and share one AES encryption resource at the same time. The throughput of our design is about 588Mbps at 105MHz frequency with reasonable area requirements.

KW - 802.16e

KW - AES CCM

KW - FPGA

KW - SBOX composite logic

UR - http://www.scopus.com/inward/record.url?scp=77949536198&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77949536198&partnerID=8YFLogxK

U2 - 10.1109/ICINIS.2009.71

DO - 10.1109/ICINIS.2009.71

M3 - Conference contribution

AN - SCOPUS:77949536198

SN - 9780769538525

SP - 253

EP - 256

BT - ICINIS 2009 - Proceedings of the 2nd International Conference on Intelligent Networks and Intelligent Systems

ER -