TY - GEN
T1 - Efficient TSV Fault Detection Scheme for High Bandwidth Memory Using Pattern Analysis
AU - Bae, Kwanho
AU - Park, Jongsun
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/10/21
Y1 - 2020/10/21
N2 - For an efficient data transmission between logic die and core die in HBM DRAM, Through-Silicon-Via (TSV) is an essential part that connects stacked memories. TSV is a vertical component which cannot be found in the conventional 2D memory. It plays an important role in improving integration in 3D memory structure. However, due to its temporal variation and technological weakness, error cases occur frequently in TSV. Following this, to increase the reliability of the memory operation, fault detection and correction method for TSV is a new challenge in 3D memory. For the efficient fault correction, fault detection method that classifies hard fault and soft error has been studied. In this paper, a new TSV fault detection method using error pattern analysis will be presented. As a result, the proposed scheme shows higher detection success rate with low area overhead, compared to the conventional scheme.
AB - For an efficient data transmission between logic die and core die in HBM DRAM, Through-Silicon-Via (TSV) is an essential part that connects stacked memories. TSV is a vertical component which cannot be found in the conventional 2D memory. It plays an important role in improving integration in 3D memory structure. However, due to its temporal variation and technological weakness, error cases occur frequently in TSV. Following this, to increase the reliability of the memory operation, fault detection and correction method for TSV is a new challenge in 3D memory. For the efficient fault correction, fault detection method that classifies hard fault and soft error has been studied. In this paper, a new TSV fault detection method using error pattern analysis will be presented. As a result, the proposed scheme shows higher detection success rate with low area overhead, compared to the conventional scheme.
KW - Error-Correction-Code(ECC)
KW - High Bandwidth memory(HBM)
KW - Through-Silicon-Via(TSV)
UR - http://www.scopus.com/inward/record.url?scp=85100750578&partnerID=8YFLogxK
U2 - 10.1109/ISOCC50952.2020.9333115
DO - 10.1109/ISOCC50952.2020.9333115
M3 - Conference contribution
AN - SCOPUS:85100750578
T3 - Proceedings - International SoC Design Conference, ISOCC 2020
SP - 19
EP - 20
BT - Proceedings - International SoC Design Conference, ISOCC 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 17th International System-on-Chip Design Conference, ISOCC 2020
Y2 - 21 October 2020 through 24 October 2020
ER -