Efficient VLSI algorithm and an implementation architecture for grayscale morphology

Sung Jea Ko, Malayappan Shridhar

Research output: Contribution to journalConference article

2 Citations (Scopus)

Abstract

This paper presents an efficient VLSI architecture for the real-time implementation of grayscale morphological operations. The proposed architecture employs a bit-serial approach which allows grayscale morphological operations to be decomposed into bit-level binary operations by a bit-modification algorithm, and thus requires only p binary operation units for the p-bit grayscale signal. In this realization, grayscale opening and closing are accomplished by local rather than cascade operations, providing greatly increased data throughput. It is shown that this realization is simple and modular in structure and is suitable for VLSI implementation.

Original languageEnglish
Pages (from-to)359-369
Number of pages11
JournalProceedings of SPIE - The International Society for Optical Engineering
Volume1350
Publication statusPublished - 1990
Externally publishedYes
EventImage Algebra and Morphological Image Processing - San Diego, CA, USA
Duration: 1990 Jul 101990 Jul 12

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Computer Science Applications
  • Applied Mathematics
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Efficient VLSI algorithm and an implementation architecture for grayscale morphology'. Together they form a unique fingerprint.

  • Cite this