TY - GEN
T1 - Electrical characteristics of gate-all-around MOSFET ring oscillators using TCAD simulation
AU - Kim, Sutae
AU - Kim, Minsuk
AU - Woo, Sola
AU - Kang, Hyungu
AU - Kim, Sangsig
N1 - Funding Information:
This work was partly supported by the National Research Foundation of Korea (NRF) Grant funded by the Korean Government (MSIP) (NRF-2013R1A2A1A03070750, NRF-2015R1A2A1A15055437), by the Brain Korea 21 Plus Project in 2017, and Samsung Electronics. The first author would like to thank for their executive support: Dongwon Kim and Chul-Hong Park.
Publisher Copyright:
© 2018 IEEE.
Copyright:
Copyright 2018 Elsevier B.V., All rights reserved.
PY - 2018/7/3
Y1 - 2018/7/3
N2 - In this paper, we investigate the performance of inverters and ring oscillators composed of gate-all-around (GAA) silicon nanowire and nanosheet (NSH) field-effect transistors (FETs), compared with FinFETs, for sub-10nm logic technology applications. Our TCAD transient simulations reveal that ring oscillators with 3 stacked channels with NSH width, three times wider than the fin width, exhibit improvements of up to 22% in the oscillation frequencies. compared to a ring oscillator with FinFETs. Thus, our study provides an insight for device down-selection in the development of GAA FET technology.
AB - In this paper, we investigate the performance of inverters and ring oscillators composed of gate-all-around (GAA) silicon nanowire and nanosheet (NSH) field-effect transistors (FETs), compared with FinFETs, for sub-10nm logic technology applications. Our TCAD transient simulations reveal that ring oscillators with 3 stacked channels with NSH width, three times wider than the fin width, exhibit improvements of up to 22% in the oscillation frequencies. compared to a ring oscillator with FinFETs. Thus, our study provides an insight for device down-selection in the development of GAA FET technology.
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U2 - 10.1109/VLSI-TSA.2018.8403835
DO - 10.1109/VLSI-TSA.2018.8403835
M3 - Conference contribution
AN - SCOPUS:85050474411
T3 - 2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018
SP - 1
EP - 2
BT - 2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018
Y2 - 16 April 2018 through 19 April 2018
ER -