Embedded DRAM-Based Memory Customization for Low-Cost FFT Processor Design

Gyuseong Kang, Woong Choi, Jongsun Park

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

In this paper, we present embedded dynamic random access memory (eDRAM)-based memory customization techniques for low-cost fast Fourier transform (FFT) processor design. The main idea is based on the observation that the FFT processor has regular and predictable memory access patterns, and it can be efficiently exploited for memory customization using eDRAM. The memory customization approaches are applied to both of the pipelined and memory-based FFT architectures. In the pipelined architecture, the read wordline (RWL) coupling write assist and data packing schemes are employed to reduce the redundant RWL and wordline driving, respectively, in column-interleaved memory arrays. The memory address decoder is also simplified with thermometer code by exploiting the sequential access patterns. For the memory-based architecture, the modified cached-memory structure is employed in addition to the techniques used in the pipelined FFT architecture. The hardware implementation results of 2k-point FFT with a 0.11- μm CMOS technology show that the proposed eDRAM-based pipelined and cached-memory FFTs achieve 26.8% and 33.2% power savings over the static RAM-based FFT design, respectively.

Original languageEnglish
Article number8052523
Pages (from-to)3484-3494
Number of pages11
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume25
Issue number12
DOIs
Publication statusPublished - 2017 Dec 1

Keywords

  • 2T gain cell
  • fast fourier transform (FFT)
  • logic-compatible eDRAM

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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