An instruction cache consumes a significant amount of energy in modern microprocessors. Therefore energy efficiency as well as performance should be considered when designing instruction cache architecture, especially for embedded processors. The authors propose a new instruction cache architecture for reducing dynamic energy consumption with negligible performance degradation, unlike typical architecture-level approaches which reduce dynamic energy consumption by sacrificing performance. The proposed instruction cache is composed of two caches: a large main instruction cache and a small low-power trace cache (LPT-cache). When a request comes into the proposed cache, either main instruction cache or LPT-cache is only accessed by utilising the information from the modified branch target buffer which enables predictions with very high accuracy. The proposed technique reduces the dynamic energy consumption significantly by replacing the accesses to a large main instruction cache with those to a small LPT-cache. Simulation results show that the proposed technique reduces dynamic energy consumption by 14.6% on average with negligible performance degradation over the traditional instruction cache.
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering