Energy-aware instruction cache design using small trace cache

J. M. Kim, Sung Woo Jung, C. H. Kim

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

An instruction cache consumes a significant amount of energy in modern microprocessors. Therefore energy efficiency as well as performance should be considered when designing instruction cache architecture, especially for embedded processors. The authors propose a new instruction cache architecture for reducing dynamic energy consumption with negligible performance degradation, unlike typical architecture-level approaches which reduce dynamic energy consumption by sacrificing performance. The proposed instruction cache is composed of two caches: a large main instruction cache and a small low-power trace cache (LPT-cache). When a request comes into the proposed cache, either main instruction cache or LPT-cache is only accessed by utilising the information from the modified branch target buffer which enables predictions with very high accuracy. The proposed technique reduces the dynamic energy consumption significantly by replacing the accesses to a large main instruction cache with those to a small LPT-cache. Simulation results show that the proposed technique reduces dynamic energy consumption by 14.6% on average with negligible performance degradation over the traditional instruction cache.

Original languageEnglish
Article numberICDTA6000004000004000293000001
Pages (from-to)293-305
Number of pages13
JournalIET Computers and Digital Techniques
Volume4
Issue number4
DOIs
Publication statusPublished - 2010 Jul 1

Fingerprint

Energy utilization
Degradation
Energy efficiency
Microprocessor chips

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

Cite this

Energy-aware instruction cache design using small trace cache. / Kim, J. M.; Jung, Sung Woo; Kim, C. H.

In: IET Computers and Digital Techniques, Vol. 4, No. 4, ICDTA6000004000004000293000001, 01.07.2010, p. 293-305.

Research output: Contribution to journalArticle

@article{129537bde8e244d5b39b4398f66b37a7,
title = "Energy-aware instruction cache design using small trace cache",
abstract = "An instruction cache consumes a significant amount of energy in modern microprocessors. Therefore energy efficiency as well as performance should be considered when designing instruction cache architecture, especially for embedded processors. The authors propose a new instruction cache architecture for reducing dynamic energy consumption with negligible performance degradation, unlike typical architecture-level approaches which reduce dynamic energy consumption by sacrificing performance. The proposed instruction cache is composed of two caches: a large main instruction cache and a small low-power trace cache (LPT-cache). When a request comes into the proposed cache, either main instruction cache or LPT-cache is only accessed by utilising the information from the modified branch target buffer which enables predictions with very high accuracy. The proposed technique reduces the dynamic energy consumption significantly by replacing the accesses to a large main instruction cache with those to a small LPT-cache. Simulation results show that the proposed technique reduces dynamic energy consumption by 14.6{\%} on average with negligible performance degradation over the traditional instruction cache.",
author = "Kim, {J. M.} and Jung, {Sung Woo} and Kim, {C. H.}",
year = "2010",
month = "7",
day = "1",
doi = "10.1049/iet-cdt.2009.0049",
language = "English",
volume = "4",
pages = "293--305",
journal = "IET Computers and Digital Techniques",
issn = "1751-8601",
publisher = "Institution of Engineering and Technology",
number = "4",

}

TY - JOUR

T1 - Energy-aware instruction cache design using small trace cache

AU - Kim, J. M.

AU - Jung, Sung Woo

AU - Kim, C. H.

PY - 2010/7/1

Y1 - 2010/7/1

N2 - An instruction cache consumes a significant amount of energy in modern microprocessors. Therefore energy efficiency as well as performance should be considered when designing instruction cache architecture, especially for embedded processors. The authors propose a new instruction cache architecture for reducing dynamic energy consumption with negligible performance degradation, unlike typical architecture-level approaches which reduce dynamic energy consumption by sacrificing performance. The proposed instruction cache is composed of two caches: a large main instruction cache and a small low-power trace cache (LPT-cache). When a request comes into the proposed cache, either main instruction cache or LPT-cache is only accessed by utilising the information from the modified branch target buffer which enables predictions with very high accuracy. The proposed technique reduces the dynamic energy consumption significantly by replacing the accesses to a large main instruction cache with those to a small LPT-cache. Simulation results show that the proposed technique reduces dynamic energy consumption by 14.6% on average with negligible performance degradation over the traditional instruction cache.

AB - An instruction cache consumes a significant amount of energy in modern microprocessors. Therefore energy efficiency as well as performance should be considered when designing instruction cache architecture, especially for embedded processors. The authors propose a new instruction cache architecture for reducing dynamic energy consumption with negligible performance degradation, unlike typical architecture-level approaches which reduce dynamic energy consumption by sacrificing performance. The proposed instruction cache is composed of two caches: a large main instruction cache and a small low-power trace cache (LPT-cache). When a request comes into the proposed cache, either main instruction cache or LPT-cache is only accessed by utilising the information from the modified branch target buffer which enables predictions with very high accuracy. The proposed technique reduces the dynamic energy consumption significantly by replacing the accesses to a large main instruction cache with those to a small LPT-cache. Simulation results show that the proposed technique reduces dynamic energy consumption by 14.6% on average with negligible performance degradation over the traditional instruction cache.

UR - http://www.scopus.com/inward/record.url?scp=77954296649&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77954296649&partnerID=8YFLogxK

U2 - 10.1049/iet-cdt.2009.0049

DO - 10.1049/iet-cdt.2009.0049

M3 - Article

VL - 4

SP - 293

EP - 305

JO - IET Computers and Digital Techniques

JF - IET Computers and Digital Techniques

SN - 1751-8601

IS - 4

M1 - ICDTA6000004000004000293000001

ER -